Soekris Dam Dac

[nige2000]

OK, it's STCP not SHCP that it's reclocking but
- is this reclocking happening on the signal line coming out of the FPGA? I take it that it is - in which case I would assume other signals (data, SHCP) are also being reclocking?

its the fpga 2.8/3.1 stcp signal it reclocks only
so makes me think sync aint essential so data loads and releases and stcp been a bit of a cycle slower doesnt matter

- you will have to reclock these signals too in order to keep them all in synch
- I'm not sure what you will gain by substituting your reclocking for the one already on the board?

But having said all this I now feel that the above scenario is not what is happening - can you explain the current functioning of the board?

was thinking of applying the mod to the 1021 not the 1101 which i might try to sell on unmodded as its power implementation is the stuff of nightmares
stcp and shcp seen to be just clk signals 2.8/3.1 and 22/24mhz, oe is pulled down and mr is pulled up
only place anything exciting is happening is on DS
think were making it more complicated than it is

[jkeny]

Edit: Got rid of my ramblings as it is simple really:
Soekris has 4 banks of shift regs - each bank has 4 shift regs - one bank is handling the + signals & one bank the - signals. so we have L+ L- R+ R- outputs.

Each data bit is latched @22MHz into the DS pin on each of the 4 shift regs - in other words there are 4 parallel data bit streams coming from the fpga to the 4 shift regs in one bank. If we name the shift regs as A, B, C, D in each bank then it operates like this - on the first 22.5792Mhz clock tick shift reg A gets bit 1, shift reg B gets bit 9, shift reg C gets bit 17 & shift reg D gets bit 25. This is happening on all four reg banks simultaneously. On the next clock tick bit 2 goes into A, bit 10 into B, bit 18 into C & bit 26 into D. 8 clock ticks has loaded the shift regs in each bank with 32 bits of data. So these 32 bits are now clocked out 8 ticks of the 22.5792MHz clock later ( 2.82Mhz).

Don't know if these high speeds are needed for 44.1KHz data rates but I guess he does upsampling, etc in FPGA?

One thing that might be a problem as the timings don't allow for any slippage - if the clock loading the data into the shift regs drifts away from the clock latching the data out then we could have bits missing from the output (they wouldn't have been clocked into the shift reg in time). But he is only using 24 of the 32 bits so it gives him 8 bits of leeway.

[adolfo.a.aguiar]

I need help with my Soekris DAM1021 rev2.
Today when I turned it on, after a couple of seconds there was a big thump so I turned it off immediately.
I started measuring continuity and voltages and noticed that POWER IN +12VDC wire (upper connection in J1) disconnected.
Fixed it and powered on again. The power led lighted and I2S input locked but no audio. Then I measured J2 and some values are weird:
PWR A-: 0.82V
PWR A+: 3.45V
Instead of -5V, I read 0.22V
5V, 3.3V and 1.2V were OK.
It seems to me that at least the diode bridge failed. Is it the part identified as D2? What's its part #?
Any other idea on what could be damaged?
Thanks.

Adolfo

[nige2000]

I need help with my Soekris DAM1021 rev2.
Today when I turned it on, after a couple of seconds there was a big thump so I turned it off immediately.
I started measuring continuity and voltages and noticed that POWER IN +12VDC wire (upper connection in J1) disconnected.
Fixed it and powered on again. The power led lighted and I2S input locked but no audio. Then I measured J2 and some values are weird:
PWR A-: 0.82V
PWR A+: 3.45V
Instead of -5V, I read 0.22V
5V, 3.3V and 1.2V were OK.
It seems to me that at least the diode bridge failed. Is it the part identified as D2? What's its part #?
Any other idea on what could be damaged?
Thanks.

Adolfo

d2 is diode bridge

the power a- and a+ looks wrong

is your power supply ok?

its good you still have 5v 3.3 and 1.2 and getting lock

you can bypass the bridge just take it off and place two wires across the pads, just make sure you have polarity right

does the r2 version have the mute circuit?
maybe post a pic of the area around the raw outputs

[adolfo.a.aguiar]

Hi Nige2000,

The PSU is supplying 12.07VDC and 11.85VDC. I have A123 packs in parallel that are switched on and off by relays. The voltages at J1 are OK.
Concerning auto mute, transistors Q3 and Q4 are there.
I will try by-passing D2.

[jkeny]

Sorry I can't help troubleshoot, Adolfo - Nige is the man for that problem

BTW, I deleted my rambling post above & replaced it with what I believe is the correct explanation of how the Soekris works

[nige2000]

Sorry I can't help troubleshoot, Adolfo - Nige is the man for that problem

BTW, I deleted my rambling post above & replaced it with what I believe is the correct explanation of how the Soekris works

lol.... yea
was gonna say you were supposed to be helping me to figure it out...

but your last explanation seems more like it

looking at the fgpa caps
every shift register has its own unique DS signal from fgpa
on each row a-d shift registers there is 4 ds signals one for each and a shared shcp 22/24mhz and a stcp signal 2.8/3.1

i think this is 8x oversampled
dont think there is a way of doing nos only digital filter bypass
richard says oversampling seems to limit dynamic range

with all the questionable issues it still manages to be a good dac

[jkeny]

Sorry I can't help troubleshoot, Adolfo - Nige is the man for that problem

BTW, I deleted my rambling post above & replaced it with what I believe is the correct explanation of how the Soekris works

lol.... yea
was gonna say you were supposed to be helping me to figure it out...

but your last explanation seems more like it

haha - you have to give my brain time to ramp up to speed these days :)

looking at the fgpa caps
every shift register has its own unique DS signal from fgpa
on each row a-d shift registers there is 4 ds signals one for each and a shared shcp 22/24mhz and a stcp signal 2.8/3.1

i think this is 8x oversampled
dont think there is a way of doing nos only digital filter bypass
richard says oversampling seems to limit dynamic range

with all the questionable issues it still manages to be a good dac

Yea but if we bypass the whole fpga affair & use our own signalling into the resistor arrays that would be useful
My computer science students don't seem to be working out too well with the XMOS - it seems too difficult for them - don;t know, yet I have to meet up with them soon.
Programming the XMOS would be the way to go, I reckon.
I don't know why Soren went with 4 DS lines to each bank of shift regs - probably for speed reasons in dealing with upsampled data

My thoughts on doing a NOS version:
- I wouldn't parallel load the data into the 4 shift regs of each bank - too complicated - I would do it serially, allowing the overflow from shift reg A into B & so on - this would now take 32 bit clocks (SHCP is our bitclock & STCP the wordclock) to fill up the 4 shift regs with 32 bits of data
- a data rate of 352KHz would need a SHCP clock of 11.264MHz (that's the speed each bit would be communicated in an I2S stream)
- so 32 ticks later when all shift regs are full we would clock the bit data out the clock of 352KHz (11.264MHz/32)
- not sure if two channels will double all these values?

This would entail doing sign magnitude conversion in an XMOS chip & outputting data L+ L- R+ R-

Sign magnitude has lower distortion in low level signals so it's probably worth doing it that way

[adolfo.a.aguiar]

Problem solved.
The culprit was one of the rails of the regulator. I didn't notice it upfront because there was a battery pack float charging.

I could find only one diode bridge (D2). Where's the other?

By the way, Audio-GD DA-M1 released with 10% discount.

Regards.

Adolfo

[jkeny]

Problem solved.
The culprit was one of the rails of the regulator. I didn't notice it upfront because there was a battery pack float charging.

I could find only one diode bridge (D2). Where's the other?

By the way, Audio-GD DA-M1 released with 10% discount.

Regards.

Adolfo

Glad you sorted it!
Thanks for the head-up on the Audio-GD DA-M1 - I note the name is a nod to Soekris product names :)
Have you ordered one of these yet, Nige?
I'm interested but again on this board there's a Xilinx CPLD through which the signals are routed

Not enough info on their site.
Looks like it handles a 24bit signal - two lines of 0.1% resistors in parallel to give 0.05% accuracy but don't know the quality of these Rs
€14 less without the resistors
Looks like it's using LVC574a which looks to be a parallel input rather than serial input of the LVC595 shift reg
This parallel input is one of the functions the Xilix CPLD provides

LVC595 has double the output current (+/-50mA) of the LVC574 (+/-24mA)
Both have the same output skew time of 1.5nS - is it too small to worry about?