Tda1387....... the older the fiddle the sweeter the tune

[abraxalito]

My thinking was that we can use an IV resistor of greater than 3K3 on the secondary of a say a 1:4 trafo - giving a higher voltage output.

Yes that's do-able - using the trafo to get voltage gain, but the shunt inductance of the trafo would need to be considered too. And the fact that trafos hate DC so you'll need another path for the DAC's bias current.

By also using a voltage divider on pin 7 at lower than 1.1V we can change the volume output to what we want 1V, 2V or whatever?

The voltage on pin7 maps to the output current directly so you can have lower volume by reducing the potential on the pin yes. Think of the DAC as multiplying the digital input value (16bits) by the pin7 voltage.

With this scheme we are always lower than 1/6 of VDD at pin 7 - if that is the critical ratio?

So long as you stay below 17% of VDD I reckon you're fine.

Substituting an attenuator as the shunt R in a voltage divider could act as a volume control

Do you mean putting a switchable resistor between pin7 and 0V? If so yeah that'd work.

[jkeny]

My thinking was that we can use an IV resistor of greater than 3K3 on the secondary of a say a 1:4 trafo - giving a higher voltage output.

Yes that's do-able - using the trafo to get voltage gain, but the shunt inductance of the trafo would need to be considered too. And the fact that trafos hate DC so you'll need another path for the DAC's bias current.

would using a differential be the cleanest way to solve the bias current issue?

By also using a voltage divider on pin 7 at lower than 1.1V we can change the volume output to what we want 1V, 2V or whatever?

The voltage on pin7 maps to the output current directly so you can have lower volume by reducing the potential on the pin yes. Think of the DAC as multiplying the digital input value (16bits) by the pin7 voltage..

[/quote] the range of adjustment send very tight I.e. a small change in voltage at pin 7 leads to a large change in output voltage? So a fixed resistor with a parallel adjustable resistor would seem to be the way of limiting the range of adjustment?

With this scheme we are always lower than 1/6 of VDD at pin 7 - if that is the critical ratio?

So long as you stay below 17% of VDD I reckon you're fine.

Substituting an attenuator as the shunt R in a voltage divider could act as a volume control

Do you mean putting a switchable resistor between pin7 and 0V? If so yeah that'd work.

Yep.

[nige2000]

think ye missed my post

messin with the vref here
to be honest its hard to judge differences
a little difference in the vref voltage and the volume changes :(
made a voltage divider at 1v with melfs
thought it sounded a little duller which it would coz its lower vol hmmn......
put in a trim pot at 1.1v then definitely a little duller
put in a 5f supercap which had to be pre charged along with the trim pot and def improved the sq
removed trim pot sounds same
and now trying to figure out whether supercap in or out sounds best

when i had supercap in i tried vref = 0-2v no smoke only different vol but my iv is only 400r til i get some more suitable resistors tomorrow

maybe no low hanging fruit for me at vref?

[abraxalito]

would using a differential be the cleanest way to solve the bias current issue?

Do you mean using two DACs push-pull (one true data, one inverted) and a centre-tapped transformer primary? I think it might work. Certainly if you want more volts out then using the trafo to accept balanced in makes sense.

What would worry me is the trafo being driven from a relatively high source impedance which is guaranteed when the trafo's step up.

If you're willing to stack DACs then the I/V resistor can be reduced as you'll have more current available. With 4 DACs either side in balanced running from 6V you'd have nearly 5mA either side. But with balanced you'd not then need any step up ratio to reach the standard 2VRMS output, in fact it could be a step down. At 6V supply each DAC can swing 4V p-p so you'd have 8V p-p on the input whereas you need 6V p-p on the output.

[jkeny]

No, got all that Nige & thanks for diving into characterising the behavior of the vref, pin 7.

Pity that there's no low hanging fruit there but I'm not giving up yet - there's still a possible role for pin 7 as a neat vol control if it isn't detrimental to the sound & it's narrow range can be accommodated.

A neat vol control like this may well have a sonic benefit?

think ye missed my post

messin with the vref here
to be honest its hard to judge differences
a little difference in the vref voltage and the volume changes :(
made a voltage divider at 1v with melfs
thought it sounded a little duller which it would coz its lower vol hmmn......
put in a trim pot at 1.1v then definitely a little duller
put in a 5f supercap which had to be pre charged along with the trim pot and def improved the sq
removed trim pot sounds same
and now trying to figure out whether supercap in or out sounds best

when i had supercap in i tried vref = 0-2v no smoke only different vol but my iv is only 400r til i get some more suitable resistors tomorrow

maybe no low hanging fruit for me at vref?

[jkeny]

would using a differential be the cleanest way to solve the bias current issue?

Do you mean using two DACs push-pull (one true data, one inverted) and a centre-tapped transformer primary? I think it might work. Certainly if you want more volts out then using the trafo to accept balanced in makes sense.

What would worry me is the trafo being driven from a relatively high source impedance which is guaranteed when the trafo's step up.

I'm confused - I thought it was the other way around - a 1:2 step-up transformer will reflect back half the resistance across the secondary - is this not correct? So if I have a 3K resistor doing IV duties on the secondary windings of the 1:2 trafo, it will reflect back & present 1.5K to the 1387's Iout pins? I must be missing something?

If you're willing to stack DACs then the I/V resistor can be reduced as you'll have more current available. With 4 DACs either side in balanced running from 6V you'd have nearly 5mA either side. But with balanced you'd not then need any step up ratio to reach the standard 2VRMS output, in fact it could be a step down. At 6V supply each DAC can swing 4V p-p so you'd have 8V p-p on the input whereas you need 6V p-p on the output.

That sounds like an interesting setup - the datasheet states a max full scale current of 1.1mA for 5V - we can get above this for 6.6V & hence 5mA for 4 stacked DACs

[nige2000]

With this scheme we are always lower than 1/6 of VDD at pin 7 - if that is the critical ratio?

So long as you stay below 17% of VDD I reckon you're fine.

the way it was behaving last night seemed pretty linear
although i chickened out at 2v on vref i got the impression that as long as we wouldnt exceed max output current on the chip all would be ok
chip out put been determined by vref and i/v resistor value?
i had 440r in last night

Substituting an attenuator as the shunt R in a voltage divider could act as a volume control

Do you mean putting a switchable resistor between pin7 and 0V? If so yeah that'd work.

yes definitely would work

i got a tiny impression that providing pin 7 both voltage and alternate route to gnd by divider had a miniscule neg effect
which surely would be easily overcome by not needing volume control further down the chain

[jkeny]

With this scheme we are always lower than 1/6 of VDD at pin 7 - if that is the critical ratio?

So long as you stay below 17% of VDD I reckon you're fine.

the way it was behaving last night seemed pretty linear
although i chickened out at 2v on vref i got the impression that as long as we wouldnt exceed max output current on the chip all would be ok
chip out put been determined by vref and i/v resistor value?
i had 440r in last night

Yea & VDD limits the Vref max V?

Substituting an attenuator as the shunt R in a voltage divider could act as a volume control

Do you mean putting a switchable resistor between pin7 and 0V? If so yeah that'd work.

yes definitely would work

i got a tiny impression that providing pin 7 both voltage and alternate route to gnd by divider had a miniscule neg effect
which surely would be easily overcome by not needing volume control further down the chain

Yea, possibly with a capacitor in parallel. I'm thinking it would make for a neat volume controlled DAC driving headphones directly?

[nige2000]

Yea & VDD limits the Vref max V?

if using solely a cap on pin 7 (self powered) it is exactly 1/6 of vdd
and you can manipulate vref voltage to adjust the output current i believe also dependant on i/v r value
whenever the bag of chips arrive ill push em harder....

Yea, possibly with a capacitor in parallel. I'm thinking it would make for a neat volume controlled DAC driving headphones directly?

yes def really cool
either headphones or poweramp direct via transformer isolated + no output caps is really cool


any way of manipulating i2s to have the chips output either left right channel mono (merging l+r output)?
maybe that dont work?

[jkeny]

Yea & VDD limits the Vref max V?

if using solely a cap on pin 7 (self powered) it is exactly 1/6 of vdd
and you can manipulate vref voltage to adjust the output current i believe also dependant on i/v r value
whenever the bag of chips arrive ill push em harder....

Yea, possibly with a capacitor in parallel. I'm thinking it would make for a neat volume controlled DAC driving headphones directly?

yes def really cool
either headphones or poweramp direct via transformer isolated + no output caps is really cool


any way of manipulating i2s to have the chips output either left right channel mono (merging l+r output)?
maybe that dont work?

For balanced configuration you need inverted L & R data
You can do this by inverting I2S data line using a simple logic inverter chip giving you -L & -R data
I'm not sure what is the optimal way of connecting differential I2S data lines to the DAC chips:
1) - should L & R go to one DAC chip & -L & -R data route to another DAC chip
2) OR -L & +L go to one DAC chip & -R & +R to another chip? Although this requires a further step in slitting out the L & R channel from the I2S data stream
edit: From memory, I believe the logic circuitry used in the 1794 DDDAC can be used to separate the I2S L & R channels but needs adjustment for 16bit rather than 24bit - don't think it deals with data inversion though we could shove an inverter chip in the logic path & adjust for half cycle delay or whatever it generates?

The use of differential signals into a transformer will help cancel noise common on both legs whether external or generated inside the DAC chip. I believe that option 2 gives better cancellation of internal DAC noise (appearing on both channels) as both -L & +L channels are handled by the same DAC as are -R & +R.

It depends on how much internal noise is generated by the DAC chip & whether it's worth the trouble to address this - maybe Richard knows?