Soekris Dam Dac

[nige2000]

had a failed attempt to replace the fpga
i thought i had a chance with the hot air and a hot plate
ah well i had to try

anyway over a couple of hours i put the r3 though most of the mods and added the usb interface


sounded so damn good too i was starting to wonder was the sd card player dac with the fixed clock setup as good
but when i played the sd card setup there was no comparison needed and i just sat down

there is a slight harsh edge to the usb version
which is helped by using the fpga clk out to clock the reclocker instead of the diyinhk ndk clocks
i can only assume this is pre-aligning the i2s signals into the fpga meaning the fpga doesnt have to work as hard to reclock

soren said yesterday the fpga shift register signals are reclocked via f-f and master clock signal in the headphone dac 1101 and oem dac 1121
which should be good
i suppose we can use really bad upstream sources now with no consequence:P

[jkeny]

had a failed attempt to replace the fpga
i thought i had a chance with the hot air and a hot plate
ah well i had to try

Pity but that FPGA would be impossible to do without oven & solder paste mask. Don't throw out that board though as it would be useful for experimenting with the r2R matrix & delivering it an alternative signal - no need for that FPGA, it could be done in other ways.

anyway over a couple of hours i put the r3 though most of the mods and added the usb interface

sounded so damn good too i was starting to wonder was the sd card player dac with the fixed clock setup as good
but when i played the sd card setup there was no comparison needed and i just sat down

Nice :)

there is a slight harsh edge to the usb version
which is helped by using the fpga clk out to clock the reclocker instead of the diyinhk ndk clocks
i can only assume this is pre-aligning the i2s signals into the fpga meaning the fpga doesnt have to work as hard to reclock

soren said yesterday the fpga shift register signals are reclocked via f-f and master clock signal in the headphone dac 1101 and oem dac 1121
which should be good
i suppose we can use really bad upstream sources now with no consequence:P

hehe, yep throw any ol' crap at it & it will shine - good marketing though :) problem is how clean is the master clock arriving at the F-F's? It is generated in the FPGA & passes through a cap on the way to F-F's - is that correct?

[nige2000]

had a failed attempt to replace the fpga
i thought i had a chance with the hot air and a hot plate
ah well i had to try

Pity but that FPGA would be impossible to do without oven & solder paste mask. Don't throw out that board though as it would be useful for experimenting with the r2R matrix & delivering it an alternative signal - no need for that FPGA, it could be done in other ways.

i dont think its impossible any of these bigger parts with multiple pads seem to slip into place at reflow temp once placed near enough
its those 603 pps caps that are ***kers they'll turn upside down and every damn thing

im just wondering did i lift a pad cleaning them

yea ill keep them alright theres two damaged boards now

anyway over a couple of hours i put the r3 though most of the mods and added the usb interface

sounded so damn good too i was starting to wonder was the sd card player dac with the fixed clock setup as good
but when i played the sd card setup there was no comparison needed and i just sat down

Nice :)

there is a slight harsh edge to the usb version
which is helped by using the fpga clk out to clock the reclocker instead of the diyinhk ndk clocks
i can only assume this is pre-aligning the i2s signals into the fpga meaning the fpga does not have to work as hard to reclock

soren said yesterday the fpga shift register signals are reclocked via f-f and master clock signal in the headphone dac 1101 and oem dac 1121
which should be good
i suppose we can use really bad upstream sources now with no consequence:P

hehe, yep throw any ol' crap at it & it will shine - good marketing though :) problem is how clean is the master clock arriving at the F-F's? It is generated in the FPGA & passes through a cap on the way to F-F's - is that correct?

Soren is very sparing with his info so i dont know if its a fpga derived clk or not, id suspect it is though multiple fpga pins to get round the shift registers? either way the elephant is still in the room but who knows maybe fpga reclocking will help

on the pics on soekris.dk i still cant see the f-f on the shift register signals on the relevant boards if he stated it today i would have thought he was taking the piss
maybe the photos are old

[Val33]

I've now got my Dam DAC and have started playing with it. I am just running it on +/-12v from a TP Placid to start with. I was not too keen to start with, but 48hrs of burn in has improved things dramatically :) Lifepo4 power will follow shortly!

I've started removing components not required, op-amps for the output, c135/142 and thought I'd also remove the input isolators. This has induced a curious problem. I am feeding the dac from a Rpi3 with Hifiberry Dac+ Pro that is all powered with Superteddy regs. Removing the isolators causes the Rpi to fail to start. Debugging, I find that as soon as the ground and data pins are connected to the Dam the Rpi behaves as if there is a dead short on its power circuit.

I guess this is a quirk of the Rpi so it seems I'll have to reinstall the isolators for now, unless I've missed something?

Val

[nige2000]

I've now got my Dam DAC and have started playing with it. I am just running it on +/-12v from a TP Placid to start with. I was not too keen to start with, but 48hrs of burn in has improved things dramatically :) Lifepo4 power will follow shortly!

I've started removing components not required, op-amps for the output, c135/142 and thought I'd also remove the input isolators. This has induced a curious problem. I am feeding the dac from a Rpi3 with Hifiberry Dac+ Pro that is all powered with Superteddy regs. Removing the isolators causes the Rpi to fail to start. Debugging, I find that as soon as the ground and data pins are connected to the Dam the Rpi behaves as if there is a dead short on its power circuit.

I guess this is a quirk of the Rpi so it seems I'll have to reinstall the isolators for now, unless I've missed something?

Val

would be great if you could post some clear pics as it helps explain the situation and rule out the simple stuff

im not really a fan of rpi as an i2s source it wouldn't be in my recipe for best sound possible, but i can understand the need for convenience

your curious problem is odd
if there's no short on the power rpi or the soekris separately there can't be when gnd and i2s connected unless your connecting gnd to 3.3 on soekris possibly

[nige2000]

i tried to put a fixed clock on top of the adjustable clock so i could do a demo with a few guys of fixed vs stock clock but it wouldn't work/lock although not powered the adjustable must be interfering
there's no comparison to fixed clk so you' ll just have to take my word for it

see pic above is a handy way of getting clean 3.3 with severing the 3.3v coming in on that 1.2r
there is evidently noise on the 3.3v going into the clock as stock as this cleans the sound quite a bit
however all my dams will be fixed clock eventually

[Val33]

hi Nigel,

Thanks for the reply, no pics at the minute as I have reinstalled the isolators but I checked everything and could find no solder bridges or wiring errors but it looks like I may be joining the 'dead board club'. With the isolators refitted I am getting no sound out, but am getting a steady lock LED. When I try to connect to umanager I get no response to "+++", but do get

Code: Select all

R1.06
L000
F7
V+00
I0

when I power up the board. I assume that V+00 is the reason for no sound! but I've no idea how it got set to that?

I guess something has corrupted the STM32? (Yes, I have had manager working previously!), Any ideas?
I'll order a ST-LINK/V2 and see if I can re-programme it following these instructions http://www.moredamfilters.info/content/replacement-way

I wanted to try the Rpi with the Hifiberry dual clock board. I've also got a BBB with TP Cronus to compare with. I only use digital to stream from my NAS or have on 'jukebox' duty. Serious listening is normally all vinyl.

Val

[nige2000]

hi Nigel,

Thanks for the reply, no pics at the minute as I have reinstalled the isolators but I checked everything and could find no solder bridges or wiring errors but it looks like I may be joining the 'dead board club'. With the isolators refitted I am getting no sound out, but am getting a steady lock LED. When I try to connect to umanager I get no response to "+++", but do get

Code: Select all

R1.06
L000
F7
V+00
I0

when I power up the board. I assume that V+00 is the reason for no sound! but I've no idea how it got set to that?

I guess something has corrupted the STM32? (Yes, I have had manager working previously!), Any ideas?
I'll order a ST-LINK/V2 and see if I can re-programme it following these instructions http://www.moredamfilters.info/content/replacement-way

I wanted to try the Rpi with the Hifiberry dual clock board. I've also got a BBB with TP Cronus to compare with. I only use digital to stream from my NAS or have on 'jukebox' duty. Serious listening is normally all vinyl.

Val

id be inclined to think the stm32 might be ok once its blinking on startup
it is blinking aint it?

i think v+00 is vol level

is there a short on the 3.3v rail on the dam

[alecm]

OK, thanks but I'm not sure what this is a graph of (or many graphs overlaid)? I presume you changed all out-of-spec resistors & you are getting no reduction in harmonics but rather random increases in different harmonics?

so matching the resistors doesnt resolve or stablise?

thanks for replying,

1. initially i have experimented a lot with changing of different resistors(to much worse values) and saw significant decreasing of harmonics. So the logic works in reverse side.

2. but when i have started to correct to the better values from mathematical calculation, i didn't received the explicit results. I received the strange behavior of harmonics based on random.

3. possibly i didn't understand how r2r matrix works to the end. so i asking you to help to find out.

[Val33]

id be inclined to think the stm32 might be ok once its blinking on startup
it is blinking aint it?

i think v+00 is vol level

is there a short on the 3.3v rail on the dam

Yes, it blinks on power up and is solid when playing music

yes, I too think v+00 is volume level and it should be v+99

I've just put the meter on the 3.3v, measures 3.8kOhm to earth?

Val