What I have read in the main thread is that the I2S MCLK OUT is designed to work in conjunction with I2S FSEL IN with sources that can accept a master clock input such as the Amenaro or BeagleBone Black running the right driver. Then the source device sends the clock frequency family to the DAM via the I2S FSEL IN and receives the clock via the I2S MCLK OUT. While the I2S MCLK OUT (n FPGA MCLK OUT) do appear to be working, AFAIK the I2S FSEL IN is not activated as of the current firmware revision. Due to the clock signal output working, some have reported some success in using that to sync their source device, but of course they can't have an automatically controlled source sampling rate clock family change... I suspect it works ok for some setups, but with some glitching noises at the changeover.nige2000 wrote:id imagine theres a clock switch option to be implemented yet in future fpga firmwarerandytsuch wrote:I haven't, but I have not seen anywhere where he said you could feed a clock to the FPGA.Val33 wrote: <SNIP>
Thanks for the reply, but the next pin is labeled as FPGA MCLK OUT.
Just wondered if anyone had confirmed that it did not work?
Val
Everything I've seen is that you can't feed an external clock into this DAC.
I have not seen any explanation for the FPGA MCLK OUT, I suspect it was initially designed to use in syncing multiple boards together when run in Dual Mono or Crossover modes, but Soren has indicated that they will work in that mode without clock syncing.
I have not seen anything about feeding the clock into the DAM in the main thread, except on people's wish lists.
Greg in Mississippi