DIY Regen Battery tweak

[randytsuch]

Out of the box suggestion for you Nige

I read at diyaudio sometime ago that you can use caps to basically make a "voltage divider" for a clock signal.

I was planning to try using some surface mount npo caps, but film sm might be better.

You would calculate the values like you would for a resistor divider. So, you could take a 3.3V clock signal, and with two caps, divide it down to 1.8V.
If you used two equal value caps, you would divide by 2 to get a 1.65V signal, which might be close enough.

Randy

[jkeny]

Yea, as I said to Nige, there are too many variables in his current setup to evaluate this idea
- 1.8V 48MHz clock is powered directly from XMOS chip (on DIYINHK board) & this is then divided to 24MHz with a flip flop & sent to USB hub chip (which normally uses 3.3V clock signal)
- comparing it to a USB hub chip with 24MHz clock, both powered by 3.3V battery + DIYINHK board powered from ?

So different powering of clocks, low voltage clock signal going to USB hub chip & length of clock signal line to USB hub chip

I was wrong before in what I posted - the Amanero uses a 1.8V 12MHz USB clock & not a 3.3V clock - so it's not an easier solution!

So a 48Mhz clock & flip flop clock divider on a separate board powered by 3.3V battery could use a flip flop to feed a 3.3V 24MHz clock signal to USB hub chip. Yea, Randy's idea of a cap based voltage divider is cool - use it to feed a 1.65V 48Mhz clock signal to the XMOS chip (or Arm chip on Amanero board)

Anyway, I figured the advantage of this synchronous clocking would be to make it easier on the final USB receiver in the XMOS (or Amanero) - relieving the USB PLL in the XMOS or Arm chip of continually matching the local clock to the incoming USB clock. It might turn out that there is no sonic advantage to this This locking of the USB clock doesn't stop the chip from using it's asynch FIFO & PLL but it may improve SQ?

[randytsuch]

I found the post with the capacitor divider recommendation.

It was by Rod Coleman (known for his DHT power supply) at diyaudio

http://www.diyaudio.com/forums/digital- ... ost4049738

[nige2000]

I found the post with the capacitor divider recommendation.

It was by Rod Coleman (known for his DHT power supply) at diyaudio

http://www.diyaudio.com/forums/digital- ... ost4049738

i forgot about that
ill try that soon

i have a ordinary resistor voltage divider providing power to the potato 7474 f-f and the ndk 48mhz clock i removed from the diyinhk board the 48mhz is fed back to the diyinhk board
the 24mhz is fed into yet another usb hub

definite improvement with this cleaner powered system

[jkeny]

i forgot about that
ill try that soon

i have a ordinary resistor voltage divider providing power to the potato 7474 f-f and the ndk 48mhz clock i removed from the diyinhk board the 48mhz is fed back to the diyinhk board
the 24mhz is fed into yet another usb hub

definite improvement with this cleaner powered system

Cool that it's an improvement - do you think it's mostly from the cleaner power for 48MHz clock? Any idea if synchronous clocking has an effect?

BTW, Randy's link gives an easier calculation than the one I gave you C1/(C1+C2) is the fraction of 3.3V that is delivered - just need to be aware of the current passed

[randytsuch]

i forgot about that
ill try that soon

i have a ordinary resistor voltage divider providing power to the potato 7474 f-f and the ndk 48mhz clock i removed from the diyinhk board the 48mhz is fed back to the diyinhk board
the 24mhz is fed into yet another usb hub

definite improvement with this cleaner powered system

Cool that it's an improvement - do you think it's mostly from the cleaner power for 48MHz clock? Any idea if synchronous clocking has an effect?

BTW, Randy's link gives an easier calculation than the one I gave you C1/(C1+C2) is the fraction of 3.3V that is delivered - just need to be aware of the current passed

I ordered some caps today for the FPGA, and planned to use them here too.

I'm going to try 100pf and 120pf, which should give me 1.8V out from a 3.3V clock. I wasn't real worried about the current through the caps, figured it would be low for this application.

I also decided that I need to buy some low temp solder paste to mount the chip, figured I need it to get the ground pad soldered down. I have a heat gun to heat it with, or else I can stick it in the oven when the wife's not looking :)

I was looking at the pics, to see how things are connected.

I can't tell if pins 18 and 19 are tied to +3.3V?
17 is for sure, which makes sense, reset needs to be pulled up.

Randy

[nige2000]

i forgot about that
ill try that soon

i have a ordinary resistor voltage divider providing power to the potato 7474 f-f and the ndk 48mhz clock i removed from the diyinhk board the 48mhz is fed back to the diyinhk board
the 24mhz is fed into yet another usb hub

definite improvement with this cleaner powered system

Cool that it's an improvement - do you think it's mostly from the cleaner power for 48MHz clock? Any idea if synchronous clocking has an effect?

well ive tested no pre usb reclocking vs asynchronous hub reclocking powered direct from battery
reclocking was a definite improvement here
then i did asynchronous reclock as above vs synchronous reclock via f-f frequency divider powered by xmos 1.8v (meaning both the 48mhz clock and f-f is powered onboard xmos 1.8v)
this was more like one step forward one step back
i could hear merit in both methods (i was leaning towards synchronous albeit a small lost in detail
providing a new 1.8v is more like the best of both in the last test
running the clk and the f-f might might be better at 3.3v its lucky that the ndk clks have a wide vcc range

BTW, Randy's link gives an easier calculation than the one I gave you C1/(C1+C2) is the fraction of 3.3V that is delivered - just need to be aware of the current passed

should be able to cobble up something here to test that

a simpler dac might be easier/better for testing this stuff

[nige2000]

[nige2000]

I can't tell if pins 18 and 19 are tied to +3.3V?
17 is for sure, which makes sense, reset needs to be pulled up.

Randy

i pulled up 18 and pulled down 15
left 17 and 19 nc

[rickmcinnis]

I am really confused here.

Are Nigel and Randy making their own REGENs or does this apply to the REGEN?