Soekris Dam Dac

[nige2000]

Right that's rows 1,2,3,4,5,6,7,8 replaced with 1nf caps

https://ie.farnell.com/panasonic-electr ... %2Fd7WU%3D

Sounds excellent very liquid free flowing
I didn't get time to do a-b comparisons with other DAC but I think this will be another area of improvement

BTW this was a pain in the arse to replace

Had a couple of scares today
Blew a couple of resistors off the ladder with the hot air
And one of the Caps I put on well just wasn't soldered good so one of the channels didn't work till I fixed it

All part of the joys

[nige2000]

Nigel,

I know you know what those caps are for but after placing 16 wires to the proper side of them I did not want to start over again!

well if yor going to wire direct to these caps from cells it might not matter as much

But as one thinks about it - the voltage across those caps is the voltage that becomes the output signal so using what we know from analogue audio, and at this point in the board it is, for all intents and purposes, analogue so using that twisted, useful only for audio, logic, I can see (can't yet hear) that you are right.

Are you removing both caps at each shift register?

i did, they are evidently a bottleneck

I found some T)220 fixed 1.2 volt LDO regulators but they have a max dropout of approx. 0.5 volt. Does that sound plausible? Seems like they would be easier to implement than the SMD type. Would you give me you opinion?

sure sounds ok, someone should test a nimh battery vs ldo here

Thanks and take care,

[rickmcinnis]

I looked up the specs on the FPGA - looks like it can accept 3.3 volts.

Wonder if there is a need for the 1.2 volts reg?

Might get warm but then it is not working very hard ...

Still, (as I edit this comment) might be better to have it isolated from the clock supply?

[jkeny]

Rick, it needs both voltages - the 1.2V for powering it's core & 3.3V for powering everything else - vref, I/Os banks, etc.
The 3.3V powering the clock is also shared with the FPGA

As Nige's battery config to these ICs brings SQ benefits then, wiring of a battery directly to each of the 16 shift register ICs is probably the optimal way to do it & I suspect that removing the caps, in your configuration, may bring additional benefits?

[nige2000]

Rick, it needs both voltages - the 1.2V for powering it's core & 3.3V for powering everything else - vref, I/Os banks, etc.
The 3.3V powering the clock is also shared with the FPGA

was thinking that last night but was too lazy to recheck the data sheet

As Nige's battery config to these ICs brings SQ benefits then, wiring of a battery directly to each of the 16 shift register ICs is probably the optimal way to do it & I suspect that removing the caps, in your configuration, may bring additional benefits?

yea wiring each shift register would be ideal at least as a reference

anyway a-b tested this morning sound is definitely more free flowing with the "fpga caps" replaced with film caps
i can't say i enjoyed soldering these caps on, they don't like much heat, there frickin tiny, and with the potential for board damage
this mod definitely ain't for the feint hearted

what i noticed more so with the fpga caps mod while ab testing versus the control dac more so than just finding differences was that with the fpga mod dac i wanted to listen to one more track before switching back, that probably says more than what the "technical difference" would suggest

[jkeny]

Rick, it needs both voltages - the 1.2V for powering it's core & 3.3V for powering everything else - vref, I/Os banks, etc.
The 3.3V powering the clock is also shared with the FPGA

was thinking that last night but was too lazy to recheck the data sheet

As Nige's battery config to these ICs brings SQ benefits then, wiring of a battery directly to each of the 16 shift register ICs is probably the optimal way to do it & I suspect that removing the caps, in your configuration, may bring additional benefits?

yea wiring each shift register would be ideal at least as a reference

anyway a-b tested this morning sound is definitely more free flowing with the "fpga caps" replaced with film caps
i can't say i enjoyed soldering these caps on, they don't like much heat, there frickin tiny, and with the potential for board damage
this mod definitely ain't for the feint hearted

what i noticed more so with the fpga caps mod while ab testing versus the control dac more so than just finding differences was that with the fpga mod dac i wanted to listen to one more track before switching back, that probably says more than what the "technical difference" would suggest

Yes, there should be benefits in using good caps in this FPGA cap bank as they pass the digital signals to the shift regs & as we know, from the Regen & elsewhere, the quality of the digital signal is important for sound quality. And, as we know from the Regen, the nature of this improvement in SQ is more accross the board fluency & realism, rather than any one specific that it affects.

What smd film caps are you using here - the EC Panasonic ones seem to be well suited to this role?

[nige2000]

Rick, it needs both voltages - the 1.2V for powering it's core & 3.3V for powering everything else - vref, I/Os banks, etc.
The 3.3V powering the clock is also shared with the FPGA

was thinking that last night but was too lazy to recheck the data sheet

As Nige's battery config to these ICs brings SQ benefits then, wiring of a battery directly to each of the 16 shift register ICs is probably the optimal way to do it & I suspect that removing the caps, in your configuration, may bring additional benefits?

yea wiring each shift register would be ideal at least as a reference

anyway a-b tested this morning sound is definitely more free flowing with the "fpga caps" replaced with film caps
i can't say i enjoyed soldering these caps on, they don't like much heat, there frickin tiny, and with the potential for board damage
this mod definitely ain't for the feint hearted

what i noticed more so with the fpga caps mod while ab testing versus the control dac more so than just finding differences was that with the fpga mod dac i wanted to listen to one more track before switching back, that probably says more than what the "technical difference" would suggest

Yes, there should be benefits in using good caps in this FPGA cap bank as they pass the digital signals to the shift regs & as we know, from the Regen & elsewhere, the quality of the digital signal is important for sound quality. And, as we know from the Regen, the nature of this improvement in SQ is more accross the board fluency & realism, rather than any one specific that it affects.

What smd film caps are you using here - the EC Panasonic ones seem to be well suited to this role?

yea had a hundred or so of these https://ie.farnell.com/panasonic-electr ... %2Fd7WU%3D

so thats what i used,
i really couldn't say if theres better ones out there or not (there probably is),but ive no intention of testing different cap types or values in this position its too much of a PITA ( cap type for me usually makes much more difference than cap value )
that said these panasonic caps definitely shouldn't be a bad choice

everything in the vref and shift register signal seems to be both ridiculously and ludicrously sensitive

[jkeny]

everything in the vref and shift register signal seems to be both ridiculously and ludicrously sensitive

Not really - remember we are essentially modifying the innards of a DAC & are getting at parts that normally we wouldn't be able to have any control over in an IC DAC chip - the Heineken effect :)

We saw that with the PCM1794 DAC which exposes some of it's innards to control from the outside. When I uncovered the use of a CCS on the Iref pin of this DAC which greatly improved the SQ, we were essentially doing the same thing - cleaning up the current reference (Iref) which the output stages of the DAC chip used, much the same as the Vref is used in the Soekris DAC. The quality of this reference (current or voltage) is the most crucial part of any DAC.

The necessary role that the bank of caps are performing between the FPGA & the shift registers is to act a voltage level shifter which allows clock signals to pass from a positive domain of the FPGA to the negative polarity of the shift registers. If this negative polarity wasn't used we could dispense with these caps altogether which would probably improve the SQ even more, I believe.

[nige2000]

everything in the vref and shift register signal seems to be both ridiculously and ludicrously sensitive

Not really - remember we are essentially modifying the innards of a DAC & are getting at parts that normally we wouldn't be able to have any control over in an IC DAC chip - the Heineken effect :)

Ah now come on!!!
if i change or remove a few caps and it turns the sound inside out id call it pretty darn sensitive :)

We saw that with the PCM1794 DAC which exposes some of it's innards to control from the outside.

without doubt we certainly have more to play with than we do with an IC dac chip

When I uncovered the use of a CCS on the Iref pin of this DAC which greatly improved the SQ

yes you noticed the guys at k&k (rakk) that figured out irefs importance, we didn't know what their implementation was we had to figure out a way or another hopefully better way to do it

we were essentially doing the same thing - cleaning up the current reference (Iref) which the output stages of the DAC chip used, much the same as the Vref is used in the Soekris DAC. The quality of this reference (current or voltage) is the most crucial part of any DAC.

yes without doubt since the first vref mod on this dac i did i thought vref on soekris and iref on 1794 are both sides of the same coin

The necessary role that the bank of caps are performing between the FPGA & the shift registers is to act a voltage level shifter which allows clock signals to pass from a positive domain of the FPGA to the negative polarity of the shift registers. If this negative polarity wasn't used we could dispense with these caps altogether which would probably improve the SQ even more, I believe.

yea thats why i wanted to bridge them,
wonder could we bridge some of them?
maybe rows 1,2,7,8?

[rickmcinnis]

I was looking at the wrong chip.

3.3 V would destroy the one installed.

Sorry about the hastiness.

Doesn't need much current.

Think I will go with a battery.

Hoping someone rents those SMD tweezers - can't imagine,me, using hot air to remove the caps without making a mess.