Tír Na HiFi

when I say the SI gets worse, I mean that when you change cables the SI at the receiver can change significantly.

High speed serial receivers really do increase their power draw a lot as the SI degrades. The "frontend" of all of these devices consists of digitally controlled analog filters. Most of them have several filter blocks that can be turned on or off as needed, and each block can have it's parameters adjusted on the fly as needed. These filters pre-process the input signal to try and get rid of the noise, reflections etc. These types of filters are what has made high speed serial interfaces viable at all.

When the SI is very good minimal filtering is needed, which uses only a small amount of power. As the SI worsens the filter parameters are changed, which increases current. As it gets worse more blocks are brought "on line" doing different types of filtering. There are control loops that constantly monitor the SI and adjust the filter system to get the best results at the "one/zero" detector.

As each of these steps occurs more and more current is required, at it's maximum the filter system can use 4 times as much current as it does at minimum. Of course the digital parts of the system take current as well, but the analog part consumes most of the power of the whole "receiver". The result is about a 3 to 1 difference in power depending on the SI of the input signal.

This SI vs. power becomes an interesting optimization strategy for some of the chips I work on. Several of them have a large number of these interfaces (hundreds), they consume a huge amount of power at lower SI, so it turns out to be cheaper to use very expensive cables ($700 cables!) so the receivers don't have to run at their full filter capability, thus using a lot less power, which means cheaper packages, smaller heatsinks, less air flow etc.

So the answer is, yes they really do "work harder" at lower SI.

Some of the lower frequency receivers don't use the analog frontends at all, they just run the input signal into a very fast ADC and use DSP to try and extract the signal from the muck. Even these change power with varying SI, but not as much as the ones with the analog frontend.

SATA is definitely in the analog frontend teritory (as is PCIe). USB HS (only 480MHz) is so slow it doesn't even use the ADC and DSP approach, although it might actually wind up being better to implement it that way today.

sbgk wrote:magnets were for educational purposes only

does the theory account for the lack of digital noise when silence is played ie all the instructions are running, only 0s are being copied ? the digital noise is only heard when there is a payload and seems to be variable with the frequency. Does a constant tone have noise issues or is it where frequencies change ?

jkeny wrote:Executive summary: Most high-speed digital receiver chips have adaptive, digitally controlled analogue filter front-ends inside the chips (maybe DaveF can confirm this or not). These filters are role is to pre-filter the signal to eliminate noise, reflections, etc. to a certain level. As the signal integrity gets worse more layers of these filters are invoked/turned on thus consuming gradually more power as the SI gets worse. I suspect that being dynamic, these filters are dynamically drawing power rather than it being a continuous draw. This dynamic draw on power (& ground return currents) can have system wide influences with ground references which are widely used in digital audio.

DaveF wrote: Yes, I've worked a few high speed rx's where there is adaptive equalisation on the incoming signal, but we'd be talking about signals in the GHz region. Digital filters tend to be running all the time from any of the implementations I've seen but perhaps there are designs out there that switch in and out different filters depending on the scenario. I have to say though that I've never come across extra power draw or fluctuations from any of this especially if something just to filter out noise above a certain frequency.
Signal integrity is something I've gone through quite a bit of in the last few months but more on the digital and FPGA side of things.

jkeny wrote: Also variations in the square wave waveform structure, rise, fall times may well be of significance

DaveF wrote:

jkeny wrote: Also variations in the square wave waveform structure, rise, fall times may well be of significance

Never seen the waveform structure vary at all regardless of what load was on the system and I've scope out all sorts of boards over the years. The PCB designers generally do extensive testing on the signals or if not they really should. If rise/fall times/skew dont seem to be correct then component changes usually sort that out. But variances, never seen it. The exception to that is jitter.