Tír Na HiFi

thought id get the scope out before goin any further the dmm sees only so much

i had thought it was the shcp signal 22/24 that was been reclocked on the dam 1101 but i was wrong it isnt
its the shcp 2.8/3.1mhz (suppose thats bclk) reclocked by 44/49mhz clk via flip flop
nothing been fed back into fgpa afaik
shcp and stcp seem to be just clk signal unless my scope cant see data
although i can see data on serial data input DS pin though at 22mhz odd

would have thought it was the shcp that would have been first priority for reclocking

http://www.nxp.com/documents/data_sheet/74LVC595A.pdf

http://www.nxp.com/documents/data_sheet/74LVC1G79.pdf

actually more confused now than i was yesterday

My guess is that it's the OE (output enable) signal that is crucial - this is the latching signal that is sent concurrently to each of the 595 chips & outputs the data.
Any skew between this OE signal (or jitter on this signal) going to each chip would cause slight mistiming of the outputs of the 595 chips so this might be the signal to reclock.

The other SHCP & STCP signals are just latching each data bit into the 595 flip-flop & latching it to the output registers, AFAIK so these are not affecting the timing of the output

hmmn.........
OE goes to 1k to gnd
so not even part of the equation

think ill try external bclk and/or mclk see if the damn thing still works

Not sure it's not part of th equation - here's what the datasheet says

"The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW."

Have a look at the logic diagram in the datasheet - it shows OE controls Q0 to Q7 output

So when OE goes low the data is output - it looks like the OE line is kept high (hence the 1K to ground so as not to draw excess current during the high stage) until data is needed to be output

jkeny wrote:Not sure it's not part of th equation - here's what the datasheet says

"The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW."

Have a look at the logic diagram in the datasheet - it shows OE controls Q0 to Q7 output

So when OE goes low the data is output - it looks like the OE line is kept high (hence the 1K to ground so as not to draw excess current during the high stage) until data is needed to be output

where would an oe signal come from only from the fpga theres only one row of caps and cant find it
all the oe pins in each row is merged
and all i see on the scope during playback is gnd noise

nige2000 wrote:

jkeny wrote:Not sure it's not part of th equation - here's what the datasheet says

"The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW."

Have a look at the logic diagram in the datasheet - it shows OE controls Q0 to Q7 output

So when OE goes low the data is output - it looks like the OE line is kept high (hence the 1K to ground so as not to draw excess current during the high stage) until data is needed to be output

where would an oe signal come from only from the fpga theres only one row of caps and cant find it
all the oe pins in each row is merged
and all i see on the scope during playback is gnd noise

Yea, I'd expect all the OE pins form each chip are connected together but there should be a signal from the FPGA - how else does it output the data bits?
We are missing something here, I reckon but what?

OK, if the OE is always kept low then the way it must work is that when STCP goes high it would normally put each data bit in the output registers but this immediately now goes to output.

So, yea, it's the STCP you want to reclock

So if I'm following you, the new Soekris has reclocking of SHCP signal before the caps using 44/49MHz clock?
Are they the only signals that are reclcoked?

You want to do this reclocking after the caps but using your own clocks & your own caps?

nope cant find a connection between oe and fpga

have to assume oe is constant on

so shcp quality is irrelevant ok

ill definitely try something with this

jkeny wrote:So if I'm following you, the new Soekris has reclocking of SHCP signal before the caps using 44/49MHz clock?
Are they the only signals that are reclcoked?

nope i had it wrong the first time
it is stcp that it reclocks from 44/49mhz

You want to do this reclocking after the caps but using your own clocks & your own caps?

yea has to be crucial, to be able provide clk signal unaffected from the chaos of the fpga and noise
maybe i can try feed it bclk from i2s as a test or just reclock fpga stcp with ff with mclk

OK, it's STCP not SHCP that it's reclocking but
- is this reclocking happening on the signal line coming out of the FPGA? I take it that it is - in which case I would assume other signals (data, SHCP) are also being reclocking?
- you will have to reclock these signals too in order to keep them all in synch
- I'm not sure what you will gain by substituting your reclocking for the one already on the board?

But having said all this I now feel that the above scenario is not what is happening - can you explain the current functioning of the board?