Home Trial offer of modified Hiface USB devices

[Fran]

ESS require a NDA to be signed to get the datasheet, but even then the details are scant I believe - isn't that correct john?

[jkeny]

ESS require a NDA to be signed to get the datasheet, but even then the details are scant I believe - isn't that correct john?

I believe the NDA has been lifted but the datasheet details are scant, anyway

[DaveF]

John,
Is there any fancy digital filtering going on prior to or in the DAC itself or does this analogue sound that Ivor describes come more from analogue output stage of your device?

The DAC is an ESS DAC & all the details of it's operation are not known. In this configuration it is operating in synchronous mode so there is no up-sampling of the signal taking place - the DAC is processing the raw audio stream. The outputs stage is another mystery & is within the DAC chip itself, no tubes, no transformers, etc.

Interesting alright. Warmth, musicality, analogue sound have no real meaning in the digital world as it's just a collection of raw bits but certain digital filtering could 'prep' this data in such a way as to give a more rounded sound after the conversion stage which could very well be described as an analogue sound. Is it a trait of the ESS DAC to have this kind of sound(other DIY'ers opinions?) or do you believe you have acheived this sound(intentionally or otherwise) outside of the DAC chip on the PCB or elsewhere?

[DaveF]

ESS require a NDA to be signed to get the datasheet, but even then the details are scant I believe - isn't that correct john?

I believe the NDA has been lifted but the datasheet details are scant, anyway

datasheets in my experience are generally scant on implementation details which is understandable if you've got some 'secret sauce' in your design to protect.

[jkeny]

John,
Is there any fancy digital filtering going on prior to or in the DAC itself or does this analogue sound that Ivor describes come more from analogue output stage of your device?

The DAC is an ESS DAC & all the details of it's operation are not known. In this configuration it is operating in synchronous mode so there is no up-sampling of the signal taking place - the DAC is processing the raw audio stream. The outputs stage is another mystery & is within the DAC chip itself, no tubes, no transformers, etc.

Interesting alright. Warmth, musicality, analogue sound have no real meaning in the digital world as it's just a collection of raw bits but certain digital filtering could 'prep' this data in such a way as to give a more rounded sound after the conversion stage which could very well be described as an analogue sound. Is it a trait of the ESS DAC to have this kind of sound(other DIY'ers opinions?) or do you believe you have acheived this sound(intentionally or otherwise) outside of the DAC chip on the PCB or elsewhere?

No, you're thinking of this the wrong way :). What I have focused on in all my modifications to the Hiface is to reduce jitter. As I achieved more & more of this, the sound became more & more analogue-like i.e silky & smooth but without lacking any details. Now this is without any manipulation of the sound or rounding off of the HF. So this analogue sound is coming from the low jitter source of the modified Hiface.

What I believe is happening is that some distortion due to jitter is being removed (some people have a theory that this is RFI). This distortion, I believe we are used to in digital systems & mistakenly believe it to be the heightened detail of digital. My analogy is that it is like MSG (flavour enhancer) - it adds a noticeably enhanced taste sensation (which isn't there naturally) but ultimately leads to a headache. The natural flavour of food is only realised when MSG is removed. The natural sound that is on a CD is only realised when the jitter (of the playback system) is removed.

So when Ivor says that I was working towards an analogue sound, it wasn't in the sense of manipulating the sound but in removing the barriers to this natural sound being heard. If you want a technical write-up & series of scope shots on how the modifications have effected jitter PM me & I'll provide but it is too technical for here.

[tony]

Ok Ivor, I was just referring to your impressions of the test. It seemed to be quiet positive to the hiface solution. Given the quality of your cdp and system I just regarded it as a good reaction to Johns device. John you seem to be onto a winner. On my brief listen with the headphones and on frans quads I was very impressed. look forward to trying it.

[DaveF]

No, you're thinking of this the wrong way :). What I have focused on in all my modifications to the Hiface is to reduce jitter. As I achieved more & more of this, the sound became more & more analogue-like i.e silky & smooth but without lacking any details. Now this is without any manipulation of the sound or rounding off of the HF. So this analogue sound is coming from the low jitter source of the modified Hiface.

What I believe is happening is that some distortion due to jitter is being removed (some people have a theory that this is RFI). This distortion, I believe we are used to in digital systems & mistakenly believe it to be the heightened detail of digital. My analogy is that it is like MSG (flavour enhancer) - it adds a noticeably enhanced taste sensation (which isn't there naturally) but ultimately leads to a headache. The natural flavour of food is only realised when MSG is removed.

So when Ivor says that I was working towards an analogue sound, it wasn't in the sense of manipulating the sound but in removing the barriers to this natural sound being heard. If you want a technical write-up & series of scope shots on how the modifications have effected jitter PM me & I'll provide but it is too technical for here.

ah I see, the mods are on the input side of the DAC. What you say above though implies that the DAC is not immune to jitter. I wonder if the jitter is giving rise to odd order harmonics on the DAC output.
I'd love to know the PLL architecture of the DAC and how it locks on to the incoming stream. Are your jitter reduction mods effective on both the SPDIF and I2S streams?
I'd appreciate if you could PM me any technical write up and plots etc. Thanks.

[jkeny]

ah I see, the mods are on the input side of the DAC. What you say above though implies that the DAC is not immune to jitter. I wonder if the jitter is giving rise to odd order harmonics on the DAC output.
I'd love to know the PLL architecture of the DAC and how it locks on to the incoming stream. Are your jitter reduction mods effective on both the SPDIF and I2S streams?
I'd appreciate if you could PM me any technical write up and plots etc. Thanks.

The mods are to the Hiface USB-I2S converter! It feeds I2S to the ESS DAC, not SPDIF, No PLL is involved. No DAC chip is "immune" to jitter - if you know of one let me know & I will immediately stop what I'm doing :). Even the ESS DACs which are touted as being immune to jitter, are not. My jitter reduction operates on the Hiface before it's output so yes it reduces jitter on SDPIF or I2S.

Can't PM them, send me your email!

[DaveF]

No DAC chip is "immune" to jitter - if you know of one let me know & I will immediately stop what I'm doing :). Even the ESS DACs which are touted as being immune to jitter, are not.

I'm afraid I dont know any specific or commercially available DAC chips that are immune to jitter. I have however designed audio interfaces as part of a larger HDMI receiver chip before. HDMI is notoriously bad for jitter levels so I had a two stage PLL. First one was a slow locking PLL locking onto the HDMI clock and the data was stored in an intermediate buffer. The DAC then with its own clean clock would read from this buffer thus being immune from jitter on the incoming stream. Of course no clock is ever perfectly clean so it was possible that the DAC had a certain amount of jitter but not from incoming clock on the cable. Ok I've left out a few other important bits that would only complicate things but I do believe its possible to design a DAC that's in some way decoupled via buffering/separate clocking from the effects of jitter on the incoming stream. I'm surprised that there isnt any such DAC's available commercially.

[jkeny]

In your described technique, is there one problem - the asynchronous clocking which will require some form of PLL to prevent buffer under/overflow? PLLs are never as low a jitter as clocks, I believe.

Here's one with a 3 stage jitter reduction technique, which has a lot going for it. http://www.anedio.com/index.php/article ... _reduction.

It uses a Digital transformer for common mode noise reduction as the first stage, then a Wolfson WM8805 digital interface receiver using an elastic buffer & finally an ESS DAC with it's jitter reduction asynch technique as the final stage. On paper it reads very well but I'm not sure about it.