Soekris Dam Dac

[rickmcinnis]

Still wonder why the middle one is oriented differently?

Will not ever use RS232 since I have no idea what one would use it for! No more computers in my audio system unless for updating SOEKRIS firmware.

What are you using for loading music into your SD cards? Seeing all of those cheap little plastic blobs worries me. Does anyone make a really good SD writer?

Wondering if taking the USB, for the writer, from a pci-e card could make any difference? One has to make this as tweaky as possible, right? Hope this isn't the big limiter with this approach.

Whether to power the writer with a battery?

It never ends ...

[nige2000]

Serial is split between top and second iso chip and iso mlk out is on second iso

FPGA creates the language that talks to the shift registers AFAIK
We need a simpler more direct project
On my investigation earlier also noticed FPGA mclk out signal is 22 or 24 MHz and waveform didn't look too bad or more importantly not worse than the one on the i2s converter not sure if full synchronization is worth investigation what you think

[gstew]

Totally agree we need a simpler version... this one is the jackknife all-in one setup that combines what is done with 3-10 boards in other setups into one board here, but full of compromises. Off the multiple inputs, off the compromised raw DC power, off the compromised chip / clock / shift register supplies, off the output stages. AND do a simpler conversion of the I2S into the parallel format that assumes that filtering is done beforehand (which makes NOS easy). Cutting out all that's not needed could result in a much simpler processor onboard. Or if you find someone smart in logic chips, it possibly could be done entirely in silicon.

Sorry, I'm nowhere near that smart!

So the Isolated MCLK is working? Huh! What about clock select?

Synchronization is an interesting thought... feed the clock signal from your USB->I2S card directly into the clock output point of the Si clock chip? Worth a try. The main question is what the FPGA chip will do if it tries to send clock frequency adjustment signals and that doesn't happen. If it gets to the point that it glitches, it could make ugly noises on the output. OTOH, it should never get there.

If your card does not use 22/24 Mhz clocks, you'd have to divide or multiply.

And of course this only works if the clock select function is working, which you'd also have to feed to the DAM from your USB->I2S card. I've seen one post that suggests it is, but never any confirmation of that from Soren.

The other time it might produce ugly outputs is when switching from one clock frequency to the other. Does your USB->I2S also produce a mute signal that you could feed to an output mute relay setup?

My 2 cents.

Greg in Mississippi

[nige2000]

So the Isolated MCLK is working? Huh! What about clock select?

yea but its the fpga divided mclk out from the Si514
dont know what the clk select is for there is no mclk input?

Synchronization is an interesting thought... feed the clock signal from your USB->I2S card directly into the clock output point of the Si clock chip? Worth a try. The main question is what the FPGA chip will do if it tries to send clock frequency adjustment signals and that doesn't happen. If it gets to the point that it glitches, it could make ugly noises on the output. OTOH, it should never get there.

i dont think thats possible

[gstew]

So the Isolated MCLK is working? Huh! What about clock select?

yea but its the fpga divided mclk out from the Si514
dont know what the clk select is for there is no mclk input?

Synchronization is an interesting thought... feed the clock signal from your USB->I2S card directly into the clock output point of the Si clock chip? Worth a try. The main question is what the FPGA chip will do if it tries to send clock frequency adjustment signals and that doesn't happen. If it gets to the point that it glitches, it could make ugly noises on the output. OTOH, it should never get there.

i dont think thats possible

Nige,

The MCLK Out and the CLK Select are designed to be fed into an upstream device like a BeagleBoneBlack-based player (with Meiro's driver) or possibly a hacked USB->I2S interface. The CLK Select is fed from the source device to the DAM to tell it which clock family is active. The DAM then feeds the 22 or 24 Mhz clock divided down from the Si514 back via the MCLK Out. That is the way the DAM is designed to run synchronously.

What I was suggesting was trying it the other way around. One would have to de-power or remove the onboard clock, then feed the clock signal from the source to the DAM. It MIGHT work, no guarantees, and is likely only to work in a limited set of situations (likely only for one source family, like 44k ripped CDs). And it might not work or be fairly glitch (like if the FPGA program tries to adjust the clock frequency and it does not respond).

Greg in Mississippi

[nige2000]

c168 to c177 looks like just the spot to direct wire the cells pos/ neg and gnd

less resistors has to be a good thing :)

[rickmcinnis]

If only I could figure out what this means!

[nige2000]

irish talk with cryptic tongue

this new revision 3 board
in plain language these larger vias at c168 to c177 will allow for easily acess to get a dozen twisted pairs of gnd/+v and gnd/-v from cells close to these switch registers


ironically i think every resistor alters/deteriorates the sound whether in digital or analog domain
there is half the amount of resistors
therefore i think we could get this board to sound better than the ones we have currently

im waiting a price on the oem board as i could be tempted to try if price is right
as it seems wasteful to get the above r3 board and then remove many of the components

[rickmcinnis]

I did not recognize this as the new board.

I agree about there being the minimum number of components for the signal to pass through. No one can argue with that! Well, at least, no one here will!

I did use those spots for wiring in the cells but using twisted pairs will result in the use of lots of wire unless you have come up with something I cannot imagine. And then there is the wire needed for the switch.

What do you have in mind?

My decision was based upon my assumption that extra wire would be worse than not being able to use twisted pairs. I think analogous to passive component reduction ...

Larger vias? Make me think of the comment on the DIYINHK about vias adding inductance!!!! Should we mention this to SOEKRIS? And larger vias, yet? Wonder if he has measured the inductance of those traces?

[jkeny]

im waiting a price on the oem board as i could be tempted to try if price is right
as it seems wasteful to get the above r3 board and then remove many of the components

From Soren "around USD 200 in qty 100 for the dam1121-02"
"It's an improved DAC R-2R core, without the AC input power supply and without output buffers. It also have direct support for connecting multiple units together syncronous, t.ex. for balanced used."
"Same base design, but different firmware."

His pricing seems way off - it seems to need two to make balanced output but waiting on datasheet & connection diagrams to work it out