Tír Na HiFi

Clarification - I am using four batteries, not sixteen.

I am much too lazy and cheap to try that.

Nigel you win the super-human patience award for replacing those caps between the FPGA and the shift registers. I wish I could follow you there but wonder if I could ever do it.

Doesn't seem anyone rents SMD removal stuff. I was thinking the tweezers would make it easy but from what I am seeing on the web hot air is recommended. Are you using hot air and if you are what size nozzle?

i was looking at available caps and think you found the best compromise. There is not much readily available. One can get larger values, interesting they are still the same height. Makes you wonder if the smaller value makes for a better capacitor? You feel confident 1000pF is sufficient?

As always, Nigel, you leave me in awe ...

nige2000 wrote: Ah now come on!!!
if i change or remove a few caps and it turns the sound inside out id call it pretty darn sensitive :)

Sure, it's critically sensitive - maybe I misunderstood your use of "ridiculously & ludicrously sensitive" - I thought you meant it shouldn't be like this?

without doubt we certainly have more to play with than we do with an IC dac chip
yes you noticed the guys at k&k (rakk) that figured out irefs importance, we didn't know what their implementation was we had to figure out a way or another hopefully better way to do it

Edit: Actually, I looked back at our many emails on this & see that in Aug 2014, I came up with the idea of using an external constant current source (CCS) bias first & then, later, found the RAKK site which mentioned something about CCS. That one sentence buried in RAKK's description was the clue I needed that CCS was possible. . Doede's long PCM1794 DAC thread had already run for 2 years on DIYAudio & everybody was trying different makes of resistors for that Iref position. Up to that point nobody had thought of or tried a CCS on the Iref pin until I asked you to post a question about using it? That idea was eventually taken on, despite initial reticence to the concept (even from Rickmcinnis :)) & various CCSes experimented with which eventually resulted in a great sounding solution. It's surprising you remember it in the way you posted!

Anyway, I'm not sure why you isolated that part of my sentence from its continuation below - you seem to be trying to make some point? All I'm saying is that these areas of current or voltage reference are very critical & there are very good past examples of this.

we were essentially doing the same thing - cleaning up the current reference (Iref) which the output stages of the DAC chip used, much the same as the Vref is used in the Soekris DAC. The quality of this reference (current or voltage) is the most crucial part of any DAC.

yes without doubt since the first vref mod on this dac i did i thought vref on soekris and iref on 1794 are both sides of the same coin

The necessary role that the bank of caps are performing between the FPGA & the shift registers is to act a voltage level shifter which allows clock signals to pass from a positive domain of the FPGA to the negative polarity of the shift registers. If this negative polarity wasn't used we could dispense with these caps altogether which would probably improve the SQ even more, I believe.

yea thats why i wanted to bridge them,
wonder could we bridge some of them?
maybe rows 1,2,7,8?

I can't envisage how bridging some of those caps would help - I'd imagine that treating them all in the same way is more correct but who knows, we need to know more about the timing of the signals being sent to the shift regs from the FPGA & their timing relationship to one another.

rickmcinnis wrote:Clarification - I am using four batteries, not sixteen.

I am much too lazy and cheap to try that.

Sure, I knew you were not using 16 batteries :) What I meant was that running wire pairs (voltage & ground) to each shift reg from one battery would likely be better than just one connection of the battery to the banks of shift regs - the reason being that you had a more direct path for current & ground current return from the battery(s) to each shft reg rather than shared tracks for this

rickmcinnis wrote:Clarification - I am using four batteries, not sixteen.

wow that would be a reference build

I am much too lazy and cheap to try that.

Nigel you win the super-human patience award for replacing those caps between the FPGA and the shift registers. I wish I could follow you there but wonder if I could ever do it.

Doesn't seem anyone rents SMD removal stuff. I was thinking the tweezers would make it easy but from what I am seeing on the web hot air is recommended. Are you using hot air and if you are what size nozzle?

not sure its small maybe 3-4 mm just keep the fan low

i was looking at available caps and think you found the best compromise. There is not much readily available. One can get larger values, interesting they are still the same height. Makes you wonder if the smaller value makes for a better capacitor? You feel confident 1000pF is sufficient?

not exactly sure, with battery i doubt it matters much, i like the lower values

jkeny, Did not want you to think I was THAT industrious, just in case there was a misunderstanding.

Nigel, Have you left the 1.2 reg on the board or have I assumed that six legged thing underneath your board is the reg in question?

I have decided to take the easy way out with the 1.2 and ordered a BELLESON 1.2 that I can basically plug into the "test points" and use the 26650 that powers the clock. Wiring in the battery looked to be too much trouble. Yes, I know that is pathetic.

Have to get another 5 volts transformer for the float supply, anyway. Figured 6.3 V is too much for the mravica reg and only had one 5 volt on hand.

Trying to muster the courage to remove the caps at the shift registers.

jkeny wrote:

nige2000 wrote: Ah now come on!!!
if i change or remove a few caps and it turns the sound inside out id call it pretty darn sensitive :)

Sure, it's critically sensitive - maybe I misunderstood your use of "ridiculously & ludicrously sensitive" - I thought you meant it shouldn't be like this?

without doubt we certainly have more to play with than we do with an IC dac chip
yes you noticed the guys at k&k (rakk) that figured out irefs importance, we didn't know what their implementation was we had to figure out a way or another hopefully better way to do it

Edit: Actually, I looked back at our emails & see that Aug 2014, I came up with the idea of using an external CCS bias first & then, later, found the RAKK site which mentioned something about CCS. That one sentence buried in RAKK's description was the clue I needed that CCS was possible. Doede's long PCM1794 DAC thread had already run for 2 years on DIYAudio & everybody was trying different makes of resistors for that Iref position. Up to that point nobody had thought of or tried a CCS on the Iref pin until I asked you to post a question about using it? That idea was eventually taken on & various CCSes experimented with which eventually resulted in a great sounding solution.

Apologies you are right my memory of the order of events is wrong, doesnt matter anyway i didnt know what ccs was at that time

Anyway, I'm not sure why you isolated that part of my sentence from its continuation below?

your reading too much into it chill:)

All I'm saying is that these areas of current or voltage reference are very critical & there are very good past examples of this.

we were essentially doing the same thing - cleaning up the current reference (Iref) which the output stages of the DAC chip used, much the same as the Vref is used in the Soekris DAC. The quality of this reference (current or voltage) is the most crucial part of any DAC.

yes without doubt since the first vref mod on this dac i did i thought vref on soekris and iref on 1794 are both sides of the same coin

The necessary role that the bank of caps are performing between the FPGA & the shift registers is to act a voltage level shifter which allows clock signals to pass from a positive domain of the FPGA to the negative polarity of the shift registers. If this negative polarity wasn't used we could dispense with these caps altogether which would probably improve the SQ even more, I believe.

yea thats why i wanted to bridge them,
wonder could we bridge some of them?
maybe rows 1,2,7,8?

I can't envisage how bridging some of those caps would help - I'd imagine that treating them all in the same way is more correct but who knows, we need to know more about the timing of the signals being sent to the shift regs from the FPGA & their timing relationship to one another.

just wanted to discuss the possibility
if i thought it was just going to be the way i just would have went ahead and did it :)

rickmcinnis wrote:jkeny, Did not want you to think I was THAT industrious, just in case there was a misunderstanding.

Nigel, Have you left the 1.2 reg on the board or have I assumed that six legged thing underneath your board is the reg in question

I have decided to take the easy way out with the 1.2 and ordered a BELLESON 1.2 that I can basically plug into the "test points" and use the 26650 that powers the clock. Wiring in the battery looked to be too much trouble. Yes, I know that is pathetic.

Have to get another 5 volts transformer for the float supply, anyway. Figured 6.3 V is too much for the mravica reg and only had one 5 volt on hand.

Trying to muster the courage to remove the caps at the shift registers.

Yea I have to remove the old 1.2 reg yet
You don't need any fancy regulation for the battery

Removed the caps with the iron.

Not as bad as I thought it would be.

So I now see the six legged thing is the 1.2 v reg.

Amazing that thing needs so much input voltage but it can supply lots of current. Does the FPGA need much current? The BELLESON is good for 1 amp - hope that is sufficient. Baffled as to why this part was chosen. Can you surmise why SOEKRIS chose this. I guess if it was required to produce much current those traces would not be as vestigial as they are?

So am I seeing this correctly that you have left that thing intact or is that an illusion? Looks like one can clip the leads easily enough. I see, as I was about to post, that you have not removed the thing. So now the question, moot as it is, but one would think there would be some conflict between the two regs?

Sorry to be so needy. And Thanks for the help.

nige2000 wrote:Apologies you are right my memory of the order of events is wrong, doesnt matter anyway i didnt know what ccs was at that time
your reading too much into it chill:)

OK, thanks - correct attribution of ideas is always appreciated :)

Removed the 1.2 V reg.

Looks like we need to jumper between pins 3 and 6?