Tír Na HiFi

jkeny wrote: Bypass caps also allow the inevitable self-generated noise on the chip's power pins to travel a short route to ground via the caps - the best configuration. Removing this short link to ground allows the spread of this noise to unwanted areas.

Hi Lads,
I've just wandered in here out of curiosity. Interesting work going on here.

Re the caps, if you have noise on your voltage supply, you can damage your digital circuits over time if those caps are not there. That one reason why they are there, to protect the FPGA's internals. Logic errors within the FPGA wouldn't be a main concern unless the noise was really bad.

Of course if the supply voltage was really really clean you might get away with it or choose different caps so as to 'filter' your chosen frequencies to ground.

DaveF wrote:

jkeny wrote: Bypass caps also allow the inevitable self-generated noise on the chip's power pins to travel a short route to ground via the caps - the best configuration. Removing this short link to ground allows the spread of this noise to unwanted areas.

Hi Lads,
I've just wandered in here out of curiosity. Interesting work going on here.

Re the caps, if you have noise on your voltage supply, you can damage your digital circuits over time if those caps are not there. That one reason why they are there, to protect the FPGA's internals. Logic errors within the FPGA wouldn't be a main concern unless the noise was really bad.

Of course if the supply voltage was really really clean you might get away with it or choose different caps so as to 'filter' your chosen frequencies to ground.

Dave, it's not the FPGA that has the bypass caps we are talking about - it's the PS pin of each logic shifter (595) chip. There are 4 of these in each bank & 4 banks so 16 chips in all. They are split into positive & negative banks - each bank of 8 chips is powered by the same common battery power supply - one battery for positive polarity bank & one battery for negative polarity bank.

As you know logic shifter chips do serial to parallel conversion - based on a clock signal input each serial bit is clocked into the nest shift register & finally latched out of the parallel output pins based on another clock - a latch enable signal. In the Soekris DAC, the power to these chips is the voltage reference that is output at each of these latched output pins & processed through the R-2R ladder to derive the DAC's final analogue output. The quality of this power is crucial to the final sound as Nige has addressed by using clean battery power.

With all these processes happening in each of the 16 chips, I reckoned it was a model for self-generated noise & the possibility of this noise affecting the sound?

Now it seems that removing the bypass caps is not detrimental to the sound which I reckon is because of there being minimum switching (& therefore min noise) during the crucial latch enable output stage of the 595 chips - the stage at which the bit values are sent in parallel to each output pin & from there determine the cumulative voltage for the 24bit digital audio word. The only processing happening in the 595 chip at this time is this latching.

Since we have an inflow of educated people on the thread, and since ive compulsion to test everything both sensical and nonsensical
im going to ask if i bridge (remove and bridge) these caps between the fpga and the shift registers see pic below (which as jk has already stated are likely for decoupling)
can i do any damage?

bear in mind the power supply is pretty much as good as it gets


will retest the bypass caps on shift register thing later

Nige,
As I suggested - you should measure the voltage on each side of those caps to see if there is any DC voltage present during operation. This will give you an idea of what you are dealing with before making any costly mistakes.

Nigel,

I know you know what those caps are for but after placing 16 wires to the proper side of them I did not want to start over again!

But as one thinks about it - the voltage across those caps is the voltage that becomes the output signal so using what we know from analogue audio, and at this point in the board it is, for all intents and purposes, analogue so using that twisted, useful only for audio, logic, I can see (can't yet hear) that you are right.

Are you removing both caps at each shift register?

I found some T)220 fixed 1.2 volt LDO regulators but they have a max dropout of approx. 0.5 volt. Does that sound plausible? Seems like they would be easier to implement than the SMD type. Would you give me you opinion?

Thanks and take care,

jkeny wrote:Nige,
As I suggested - you should measure the voltage on each side of those caps to see if there is any DC voltage present during operation. This will give you an idea of what you are dealing with before making any costly mistakes.

I agree.

In your picture the 1st row (bottom) and 3rd row of sr's get a positive voltage, and are probably fine.

The 2nd and 4th rows get negative voltage.
For these sr's, the sr ground pin is connected to -3.3V (or -4V if its a stock board), and the sr VCC pin is connected to ground. So these sr's see a positive 3.3V across VCC and ground, but they are negatively offset versus ground of the rest of the dac.

This is probably why he has all the caps between the FPGA and the sr's. I don't think he needs the caps on the signals to the 1st and 3rd rows of sr's, guessing he did it to make everything the same.

EDIT: This would probably violate the input pin requirements on the sr's, and you could either blow them up, or they may not work correctly. I don't remember if there are any status lines (outputs from the sr's) going to the FPGA. If there are, you could blow the FPGA too, which would ruin the board.

Another edit: I figured this out the other day, looking at the sr datasheet
On the shift registers, pin definitions are:
14 is serial data in
1-7 and 15 are data outputs
8 is ground
16 is vcc
9 is serial data out
10 is reset, active low
11 is shift clock in
12 is storage register clock in
13 is output enable, active low

As long as pins 1-7, 9 and 15 don't connect to the fpga, I don't think you will blow up the fpga.
But the shift registers are another story.

Randy

randytsuch wrote:

jkeny wrote:Nige,
As I suggested - you should measure the voltage on each side of those caps to see if there is any DC voltage present during operation. This will give you an idea of what you are dealing with before making any costly mistakes.

I agree.

In your picture the 1st row (bottom) and 3rd row of sr's get a positive voltage, and are probably fine.

The 2nd and 4th rows get negative voltage.
For these sr's, the sr ground pin is connected to -3.3V (or -4V if its a stock board), and the sr VCC pin is connected to ground. So these sr's see a positive 3.3V across VCC and ground, but they are negatively offset versus ground of the rest of the dac.

This is probably why he has all the caps between the FPGA and the sr's. I don't think he needs the caps on the signals to the 1st and 3rd rows of sr's, guessing he did it to make everything the same.

EDIT: This would probably violate the input pin requirements on the sr's, and you could either blow them up, or they may not work correctly. I don't remember if there are any status lines (outputs from the sr's) going to the FPGA. If there are, you could blow the FPGA too, which would ruin the board.

Another edit: I figured this out the other day, looking at the sr datasheet
On the shift registers, pin definitions are:
14 is serial data in
1-7 and 15 are data outputs
8 is ground
16 is vcc
9 is serial data out
10 is reset, active low
11 is shift clock in
12 is storage register clock in
13 is output enable, active low

As long as pins 1-7, 9 and 15 don't connect to the fpga, I don't think you will blow up the fpga.
But the shift registers are another story.

Randy

Agreed, Randy the shift regs operating on negative voltage only work because all the input signalling is kept floating by using caps to block any DC - so pins 9 (serial data in), 10, 11, 12 & 13 all probably need to be floating? The output pins (1-7, 15 doesn't connect to anything) are OK as they only connect to the R-ladder & their compliance is not violated.

All the shift regs signal input signals arise from the FPGA, most do so directly - another reason for not bridging those caps, even on the positive polarity shift regs, as you said.

jkeny wrote:

randytsuch wrote:

jkeny wrote:Nige,
As I suggested - you should measure the voltage on each side of those caps to see if there is any DC voltage present during operation. This will give you an idea of what you are dealing with before making any costly mistakes.

I agree.

In your picture the 1st row (bottom) and 3rd row of sr's get a positive voltage, and are probably fine.

The 2nd and 4th rows get negative voltage.
For these sr's, the sr ground pin is connected to -3.3V (or -4V if its a stock board), and the sr VCC pin is connected to ground. So these sr's see a positive 3.3V across VCC and ground, but they are negatively offset versus ground of the rest of the dac.

This is probably why he has all the caps between the FPGA and the sr's. I don't think he needs the caps on the signals to the 1st and 3rd rows of sr's, guessing he did it to make everything the same.

EDIT: This would probably violate the input pin requirements on the sr's, and you could either blow them up, or they may not work correctly. I don't remember if there are any status lines (outputs from the sr's) going to the FPGA. If there are, you could blow the FPGA too, which would ruin the board.

Another edit: I figured this out the other day, looking at the sr datasheet
On the shift registers, pin definitions are:
14 is serial data in
1-7 and 15 are data outputs
8 is ground
16 is vcc
9 is serial data out
10 is reset, active low
11 is shift clock in
12 is storage register clock in
13 is output enable, active low

As long as pins 1-7, 9 and 15 don't connect to the fpga, I don't think you will blow up the fpga.
But the shift registers are another story.

Randy

Agreed, Randy the shift regs operating on negative voltage only work because all the input signalling is kept floating by using caps to block any DC - so pins 9 (serial data in), 10, 11, 12 & 13 all probably need to be floating? The output pins (1-7, 15 doesn't connect to anything) are OK as they only connect to the R-ladder & their compliance is not violated.

All the shift regs signal input signals arise from the FPGA, most do so directly - another reason for not bridging those caps, even on the positive polarity shift regs, as you said.

lol just after figuring a lot of that out and was about to report:)

it seems rows 3,4,5,6 have + signal one side and - signal on the other side of the caps
so no bridging there
ill likely just try smd film caps in this section

but there is good news as i can now be more Politically Correct
and say smd film bypass caps on the shift registers have brought sq very close to no bypass caps dac

Well, that sounds like a waste of time.

Never know till you try, I guess.

Will you remove them?

nige2000 wrote:
but there is good news as i can now be more Politically Correct
and say smd film bypass caps on the shift registers have brought sq very close to no bypass caps dac

What type of smd film caps are you using, and where did you install them?
On the dac output?

Randy