Tír Na HiFi

jkeny wrote:

nige2000 wrote:

jkeny wrote:Yea & VDD limits the Vref max V?

if using solely a cap on pin 7 (self powered) it is exactly 1/6 of vdd
and you can manipulate vref voltage to adjust the output current i believe also dependant on i/v r value
whenever the bag of chips arrive ill push em harder....

Yea, possibly with a capacitor in parallel. I'm thinking it would make for a neat volume controlled DAC driving headphones directly?

yes def really cool
either headphones or poweramp direct via transformer isolated + no output caps is really cool


any way of manipulating i2s to have the chips output either left right channel mono (merging l+r output)?
maybe that dont work?

For balanced configuration you need inverted L & R data
You can do this by inverting I2S data line using a simple logic inverter chip giving you -L & -R data

yea im down with that i was just trying to complicate things further by making the chips mono
i.e 4 chips L+,L-,R+,R-

I'm not sure what is the optimal way of connecting differential I2S data lines to the DAC chips:
1) - should L & R go to one DAC chip & -L & -R data route to another DAC chip

i got it in my head that dac chips that handle two channels are compromised in terms of cross talk/noise and voltage swing affecting dynamics and detail
just a theory though could be wrong :)

2) OR -L & +L go to one DAC chip & -R & +R to another chip? Although this requires a further step in slitting out the L & R channel from the I2S data stream

i have the remains of the logic of a rehashed version of the dddac 1794 i could test that

edit: From memory, I believe the logic circuitry used in the 1794 DDDAC can be used to separate the I2S L & R channels but needs adjustment for 16bit rather than 24bit - don't think it deals with data inversion though we could shove an inverter chip in the logic path & adjust for half cycle delay or whatever it generates?

i dont think 16 or 24bit input matters, seems to work at 24bit input (in software selection), i think :)
does a inverter chip not cause a half cylce delay needing a shift register to realign?

The use of differential signals into a transformer will help cancel noise common on both legs whether external or generated inside the DAC chip. I believe that option 2 gives better cancellation of internal DAC noise (appearing on both channels) as both -L & +L channels are handled by the same DAC as are -R & +R.

yea like that idea too

It depends on how much internal noise is generated by the DAC chip & whether it's worth the trouble to address this - maybe Richard knows?

maybe just try and see:)

Yea, I see - maybe 4 DAC chips each one handling one of the channels L+ L- R+ R-
Would you want both outputs in each DAC chip to be handling the same signal i.e one DAC chip is outputting L+ on both outputs?
To do that you would probably require a bit more manipulation of the IS2 data & I can't think of an easy way to do it
The whole idea of differential noise cancellation might not bring much to the party - who knows - suck it & see, as you say.
I'm not sure what you are saying about 24bit? The logic circuitry for the DDDAC1794 DAC expects a 24 bit input signal & counts out 24 bit clocks before splitting out the L & R channel & aligning them - I don't think it will work if fed 16 bit data but I guess you can use a software player to always output 24bits even when playing 16 bit files - as a proof of concept, I guess?

The 1387 DACs will handle 24bit data by just lopping off the top 8 bits, I believe - 8 bits with no data in them if playing 16 bit files upconverted to 24bit

jkeny wrote:I'm confused - I thought it was the other way around - a 1:2 step-up transformer will reflect back half the resistance across the secondary - is this not correct?

Its partly correct - the ratio is N*N so a quarter of the resistance will appear at the DAC output. But also the ratio multiplies up the self-capacitance of the secondary winding to make it 4X higher. But my head's spinning given that the DAC is Iout as to what source impedance the trafo sees driving into it. I think I need a little more study....

If you're willing to stack DACs then the I/V resistor can be reduced as you'll have more current available. With 4 DACs either side in balanced running from 6V you'd have nearly 5mA either side. But with balanced you'd not then need any step up ratio to reach the standard 2VRMS output, in fact it could be a step down. At 6V supply each DAC can swing 4V p-p so you'd have 8V p-p on the input whereas you need 6V p-p on the output. That sounds like an interesting setup - the datasheet states a max full scale current of 1.1mA for 5V - we can get above this for 6.6V & hence 5mA for 4 stacked DACs

I was thinking today that perhaps a common base I/V transistor followed by a classA buffer driving the trafo would be simple and effective. Driving transformers from anything other than buffers gives me the chills... With the active I/V stage and buffer you'd not need to stack DACs. You could also fit a 2nd order LC filter between the buffer and the trafo primary to correct the NOS droop and to attenuate the images. This would then be pretty much my ultra-modded variant of the Taobao 8*TDA1387 DAC minus the complex CLCLC anti-imaging filter.

For doing I2S manipulations the easiest long-term solution is to get a microcontroller to handle it. Then you have all other possibilities available to you, only limited by software.

I've started designing a replacement for the Philips SAA7220 digital filter and plan to use a cheap ($2 or $3) ARM chip to handle it. It will be quite feasible to re-program the filter with any kind of function you can fit into the computing power (40MIPs or so) and memory available. Reformatting I2S to separate channels and/or invert would be a very easy proposition.

abraxalito wrote:For doing I2S manipulations the easiest long-term solution is to get a microcontroller to handle it. Then you have all other possibilities available to you, only limited by software.

I've started designing a replacement for the Philips SAA7220 digital filter and plan to use a cheap ($2 or $3) ARM chip to handle it. It will be quite feasible to re-program the filter with any kind of function you can fit into the computing power (40MIPs or so) and memory available. Reformatting I2S to separate channels and/or invert would be a very easy proposition.

We could do this with the XMOS DAC chip itself rather than use another chip to do these duties. I've been meaning to get to grips with XMOS programming but haven't gotten very far with it. Now if someone with experience in programming using modern development platforms, like Fryderyk was to get involved & we could get a basic root system compiled, I'm sure we could make great progress on this - I'm not so good in setting up the development platform & libraries needed for stuff like this but I'm OK with the programming, once I have a base working code to start with. Lots of code on the XMOS site to work from.

I don't fancy ARM programming at the moment. I once thought I might but not now unless it proves to be a far easier development platform than I imagine?

However, If Richard does some development work on the ARM chip, that would be a good springboard to get started with

abraxalito wrote:

jkeny wrote:I'm confused - I thought it was the other way around - a 1:2 step-up transformer will reflect back half the resistance across the secondary - is this not correct?

Its partly correct - the ratio is N*N so a quarter of the resistance will appear at the DAC output. But also the ratio multiplies up the self-capacitance of the secondary winding to make it 4X higher. But my head's spinning given that the DAC is Iout as to what source impedance the trafo sees driving into it. I think I need a little more study....

Ok, it's the square of the ratio - so 1:2 trafo reflects back 1/4 of the secondary resistance; 1:4 reflects back 1/16 of the resistance.
Yea, I wasn't sure what compliance is needed at the DAC's output pins when current output? Datasheet says that DC output voltage compliance is 3.5V max so full scale output current @5V ranges from 0.86 to 1.14mA - to remain within compliance a max resistor of about 3K is calculated. I guess with 6.6V VDD the output voltage compliance is probably > 3.5V & therefore > 3K resistor is max. I don't know if this is correct as but & 6.6V VDD let's say 2mA is max current output - does this change the output compliance V (probably not?) - then 2.3K is max resistor value?

If you're willing to stack DACs then the I/V resistor can be reduced as you'll have more current available. With 4 DACs either side in balanced running from 6V you'd have nearly 5mA either side. But with balanced you'd not then need any step up ratio to reach the standard 2VRMS output, in fact it could be a step down. At 6V supply each DAC can swing 4V p-p so you'd have 8V p-p on the input whereas you need 6V p-p on the output. That sounds like an interesting setup - the datasheet states a max full scale current of 1.1mA for 5V - we can get above this for 6.6V & hence 5mA for 4 stacked DACs

I was thinking today that perhaps a common base I/V transistor followed by a classA buffer driving the trafo would be simple and effective. Driving transformers from anything other than buffers gives me the chills... With the active I/V stage and buffer you'd not need to stack DACs. You could also fit a 2nd order LC filter between the buffer and the trafo primary to correct the NOS droop and to attenuate the images. This would then be pretty much my ultra-modded variant of the Taobao 8*TDA1387 DAC minus the complex CLCLC anti-imaging filter.

OK, I hear you about driving the trafo from buffer & incorporating a NOS droop correction & LP filter to attenuate images.

ok ive damaged one of the chips bit of buzzing on left channel
either i overloaded with iv (yea 3k3 too much went over 4vdc) or i had a blob of solder between iol and vdd
strangely enough only damaged one chip

have to get it in my head
less haste makes for more speed....
too excited i guess

jkeny wrote: We could do this with the XMOS DAC chip itself rather than use another chip to do these duties. I've been meaning to get to grips with XMOS programming but haven't gotten very far with it.

How's the current draw with the XMOS chip? I recall when I explored them a few years back their chips were really rather thirsty. And do you program them in a special kind of C?

I don't fancy ARM programming at the moment. I once thought I might but not now unless it proves to be a far easier development platform than I imagine?

However, If Richard does some development work on the ARM chip, that would be a good springboard to get started with

Its an acquired taste to enjoy ARM programming, its not for everyone. I have always loved assembly code, ever since I was a schoolboy. Can't stand C.

I'd like to create some kind of interactive 'monitor' for ARM so that we could tighten the loop between code and results, but its just a 'wouldn't it be nice' idea in my mind.

jkeny wrote:Ok, it's the square of the ratio - so 1:2 trafo reflects back 1/4 of the secondary resistance; 1:4 reflects back 1/16 of the resistance.
Yea, I wasn't sure what compliance is needed at the DAC's output pins when current output? Datasheet says that DC output voltage compliance is 3.5V max so full scale output current @5V ranges from 0.86 to 1.14mA - to remain within compliance a max resistor of about 3K is calculated. I guess with 6.6V VDD the output voltage compliance is probably > 3.5V & therefore > 3K resistor is max. I don't know if this is correct as but & 6.6V VDD let's say 2mA is max current output - does this change the output compliance V (probably not?) - then 2.3K is max resistor value?

I've been assuming the 'high end' compliance is just VDD minus 1.5V. Not sure if this is right though, I've not pushed it as now I'm convinced active I/V is the best SQ the compliance is kept very low. At 6.6V on VDD you'll have about 1.3mA as the max current.

abraxalito wrote:

jkeny wrote: We could do this with the XMOS DAC chip itself rather than use another chip to do these duties. I've been meaning to get to grips with XMOS programming but haven't gotten very far with it.

How's the current draw with the XMOS chip? I recall when I explored them a few years back their chips were really rather thirsty. And do you program them in a special kind of C?

I think in 2014 XMOS incorporated an ARM core so these chips are 200mW on 3.3V which using 2400mAh batteries is fine - about 40 hours from fully charged battery

I don't fancy ARM programming at the moment. I once thought I might but not now unless it proves to be a far easier development platform than I imagine?

However, If Richard does some development work on the ARM chip, that would be a good springboard to get started with

Its an acquired taste to enjoy ARM programming, its not for everyone. I have always loved assembly code, ever since I was a schoolboy. Can't stand C.

I'd like to create some kind of interactive 'monitor' for ARM so that we could tighten the loop between code and results, but its just a 'wouldn't it be nice' idea in my mind.

Ah, assembly code is not for me - OK in small doses, maybe :)