Tír Na HiFi

randytsuch wrote:

nige2000 wrote:think of the potential areas of sq loss
noise, jitter bottlenecks
ps is now excellent especially for vref
what remaining components are adding noise/jitter
im a fan of no digital filter, sound quality is the goal
the fpga is only a method to translate i2s into the resistor ladder
if sound quality is the ultimate goal a lot of the fpga features arent needed and if it could be done with less noise and accurately clocked in a reasonably simple fashion it should be better

Since we don't know what's in the FPGA, and these days FPGA's can contain a TON of logic, IMHO I don't think we can replace it.

Wondering if it would be possible to do a little surgery, and reclock the signals between the FPGA and the ladder section, to remove the jitter.

Randy

i very briefly put the scope on the signals between the fpga and shift registers and just got confused, lots research and learning is needed at least on my behalf to even consider either a reclock or replace

So I did a quick look at the PWB.

Looks like there are two sets of shift registers per channel, 4 total. I guess he alternates between shift register sets.
This means there are four sets of shift registers. Reclocking the data before the shift registers may help, but would be a pain to implement. It looks like there are caps on all the lines between the FPGA and shift registers (not sure why there are caps on these lines), which may be a place to break into the signals.

The signals from the FPGA to the shift registers should make more sense if you look at a LVC595 datasheet.

On the shift registers, pin definitions are:
14 is serial data in
1-7 and 15 are data outputs
8 is ground
16 is vcc
9 is serial data out
10 is reset, active low
11 is shift clock in
12 is storage register clock in
13 is output enable, active low

And for me, it will be a while until I get to the point where I would even consider messing with this. I need to work on power first. And this would take a lot of work, and be pretty easy to break your board.


Randy

Yea, a scope will only confuse - a logic analyser is what you need - this will show the signals on each line & the relative timing between them

nige2000 wrote:

randytsuch wrote:

nige2000 wrote:think of the potential areas of sq loss
noise, jitter bottlenecks
ps is now excellent especially for vref
what remaining components are adding noise/jitter
im a fan of no digital filter, sound quality is the goal
the fpga is only a method to translate i2s into the resistor ladder
if sound quality is the ultimate goal a lot of the fpga features arent needed and if it could be done with less noise and accurately clocked in a reasonably simple fashion it should be better

Since we don't know what's in the FPGA, and these days FPGA's can contain a TON of logic, IMHO I don't think we can replace it.

Wondering if it would be possible to do a little surgery, and reclock the signals between the FPGA and the ladder section, to remove the jitter.

Randy

i very briefly put the scope on the signals between the fpga and shift registers and just got confused, lots research and learning is needed at least on my behalf to even consider either a reclock or replace

randytsuch wrote:So I did a quick look at the PWB.

Looks like there are two sets of shift registers per channel, 4 total. I guess he alternates between shift register sets. This means there are four sets of shift registers.

Each Left & Right channel comprises a positive & negative going analogue signal. There are 4 shift registers for each polarity, so 16 shift registers in all. The L&R channels

Reclocking the data before the shift registers may help, but would be a pain to implement. It looks like there are caps on all the lines between the FPGA and shift registers (not sure why there are caps on these lines), which may be a place to break into the signals.

Yes that's the place to break in but reclocking is probably not so easy - the clock signal is manipulated & delayed within the FPGA

The signals from the FPGA to the shift registers should make more sense if you look at a LVC595 datasheet.

On the shift registers, pin definitions are:
14 is serial data in
1-7 and 15 are data outputs
8 is ground
16 is vcc
9 is serial data out
10 is reset, active low
11 is shift clock in
12 is storage register clock in
13 is output enable, active low

Yes, that's the place to figure out what signals are being delivered to the 595 chips.
Also note that Soren hasn't used one of the data outputs Q0 (pin 15) - probably because it's on the other side of the chip & the track from it to the resistors would be somewhat longer than tracks from Q1-Q7?

And for me, it will be a while until I get to the point where I would even consider messing with this. I need to work on power first. And this would take a lot of work, and be pretty easy to break your board.


Randy

my impression was that it will be as easy if not easier to replace the front end as to reclock it?

So no joy here :(

Connected my Amanero last night, and tried it, but could not get signal lock.

I double checked everything, it looks ok. One thing is I had to make a 3.3V supply for the isolated 3.3 and the amanero, and its a little low. I also accidentally connected it while it was hot (stupid thing I know), but I luckily connected ground first, so I think things are still working.

The Amanero still appears to work, it can talk to my PC. But the LED is flashing, and no output.

When I get more time, I may try loading the DAC firmware again, although it appears to be working. I may have to break out the scope and look at signals.

Randy

led on dac should lock when i2s signal present so no point looking for sound until its lit :)

the input pins are confusing i soldered them in wrong more than once

maybe a pic will help

have you power going to the isolators?

sorry for pointing out simple stuff but its usually what it is

nige2000 wrote:led on dac should lock when i2s signal present so no point looking for sound until its lit :)

the input pins are confusing i soldered them in wrong more than once

maybe a pic will help

have you power going to the isolators?

sorry for pointing out simple stuff but its usually what it is

I appreciate any advice you can give.

I'm at work now (its 9am my time now), I can take a picture tonight.

But I checked the pins MANY times, and even tried swapping the LR clock and bit clock signals, but that didn't work.

I think I have power on the isolators, I checked the caps to the left of the isolators, and they have 3.3V on them, or at least close to 3.3V. (Left of the isolators looking at the board with the input connector on the left, and the output on the right)

It probably is something obvious, but I can't figure it out so far.

Randy

I have lock, and music :)

Did some searching today, and saw somebody had this type of problem, and he reloaded the FPGA.

So I figured it was worth a try. I reloaded 0.99, and now it works great.

Not sure what happened. I had loaded .99 and then a filter before I connected the Amanero and couldn't get lock. This time, I just loaded .99 and left the default filter in, and it locks fine.

I listened a little, and it sounds pretty good considering I'm powering it with walwarts right now with no mods yet except for removing the output opamps.

randytsuch wrote:I have lock, and music :)

Did some searching today, and saw somebody had this type of problem, and he reloaded the FPGA.

So I figured it was worth a try. I reloaded 0.99, and now it works great.

Not sure what happened. I had loaded .99 and then a filter before I connected the Amanero and couldn't get lock. This time, I just loaded .99 and left the default filter in, and it locks fine.

I listened a little, and it sounds pretty good considering I'm powering it with walwarts right now with no mods yet except for removing the output opamps.

cool
Think that happened me before

Funny how the potential shines through the poorer ps