Tír Na HiFi

Have you found a way around the onboard isolators?

It occurred to me it would be easy enough to make voltage references similar to what SOEKRIS has used but hopefully better to charge our batteries.

I am skeptical of the AUDIOWIND regulators. Will be interesting to hear how they maintain the voltage over time. Mindless concern, perhaps ...

Brian Lowe suggested something. When I get back I will post it.

Take care,

rickmcinnis wrote:Have you found a way around the onboard isolators?

no i have not bypassed them as of yet assume its just a matter of removal and direct connection to pads

It occurred to me it would be easy enough to make voltage references similar to what SOEKRIS has used but hopefully better to charge our batteries.

my experience so far is that a bit of a skew is undetectable by ear with this battery system so theres no need to get so excited about ps voltage reference, anyway any drift i seen so far is negligible

I am skeptical of the AUDIOWIND regulators. Will be interesting to hear how they maintain the voltage over time. Mindless concern, perhaps ...

the whole point of using these batteries is that they forgive a multitude of sins, ive done lots of this sort of thing and using linear supplies to charge cells has no neg effect during playback, you can barely hear it when you use cheap smps to charge, im just too particular to do that and we are using the cell at its optimum voltage
look at this discharge graph, the cell wants to be 3.3v:)

Brian Lowe suggested something. When I get back I will post it.

Take care,

Reclocking circuit?

That is interesting. I would expect that the FPGA skew would be larger than any skew you have on the I2S signals, but if you hear a difference by reclocking than I guess not.


And my SPDIF circuit didn't work, I forgot there is other stuff I need to add, transformer, resistor and cap.

I think I'll just byte the bullet, and pull my Amanero from my ES9018 DAC, and set it up with this DAC.

Randy

randytsuch wrote:Reclocking circuit?

That is interesting. I would expect that the FPGA skew would be larger than any skew you have on the I2S signals, but if you hear a difference by reclocking than I guess not.

thb it doesnt do a lot in this configuration i think it adds a little focus but not much
if youve got any ideas how to bypass the fpga that sure would be interesting

And my SPDIF circuit didn't work, I forgot there is other stuff I need to add, transformer, resistor and cap.

I think I'll just byte the bullet, and pull my Amanero from my ES9018 DAC, and set it up with this DAC.

Randy

strange enough i favor the xmos i2s for this

Bypassing FPGA, I don't think its possible.
The FPGA is the brains of this board, so we are stuck with it.

I have an amanero already, never tried the xmos.

Guy at diy offered to sell me a amanero and the older exasound. Asked for the price for just the exasound. It was kind of expensive when it came out a few years ago.

So I'll try the exasound, or buy a xmos from diyinhk.

Randy

Attempting to feed R2R circuit of the Soekris requires other than an I2S signal.

It takes a sign magnitude signal & some control signals - shift register clock input, storage register clock input, output enable
As well as that Soren didn't use the Q7 output pin from the 595 shift register chips - he's just using Q0 - Q6 so only 7 bits per chip which means he inserts a 0bit every 7 bits in the input signal

jkeny wrote:Attempting to feed R2R circuit of the Soekris requires other than an I2S signal.

It takes a sign magnitude signal & some control signals - shift register clock input, storage register clock input, output enable
As well as that Soren didn't use the Q7 output pin from the 595 shift register chips - he's just using Q0 - Q6 so only 7 bits per chip which means he inserts a 0bit every 7 bits in the input signal

Is this if you want to bypass the FPGA?

randytsuch wrote:

jkeny wrote:Attempting to feed R2R circuit of the Soekris requires other than an I2S signal.

It takes a sign magnitude signal & some control signals - shift register clock input, storage register clock input, output enable
As well as that Soren didn't use the Q7 output pin from the 595 shift register chips - he's just using Q0 - Q6 so only 7 bits per chip which means he inserts a 0bit every 7 bits in the input signal

Is this if you want to bypass the FPGA?

Yes, these are the signal characteristics sent out by the FPGA to the R2R section. The R2R section is the part that converts the signal fro digital to analogue & comprises of the logic shifter chips (the 8 chips on each channel) & all the resistors

think of the potential areas of sq loss
noise, jitter bottlenecks
ps is now excellent especially for vref
what remaining components are adding noise/jitter
im a fan of no digital filter, sound quality is the goal
the fpga is only a method to translate i2s into the resistor ladder
if sound quality is the ultimate goal a lot of the fpga features arent needed and if it could be done with less noise and accurately clocked in a reasonably simple fashion it should be better

nige2000 wrote:think of the potential areas of sq loss
noise, jitter bottlenecks
ps is now excellent especially for vref
what remaining components are adding noise/jitter
im a fan of no digital filter, sound quality is the goal
the fpga is only a method to translate i2s into the resistor ladder
if sound quality is the ultimate goal a lot of the fpga features arent needed and if it could be done with less noise and accurately clocked in a reasonably simple fashion it should be better

Since we don't know what's in the FPGA, and these days FPGA's can contain a TON of logic, IMHO I don't think we can replace it.

Wondering if it would be possible to do a little surgery, and reclock the signals between the FPGA and the ladder section, to remove the jitter.

Randy