my post from diya
feedback from this might be interesting over there :)
put the scope on the clock output couple of days ago and was less than excited about the waveform
got me thinking that sharing one cell with the clock, fpga, microcontroller, usb to i2s device and the + vref rail might not be so hot of an idea
so i added another cell just for the vref so that +/- vref has a cell each and the 'front end" has its own cell
wouldn't mind this one was supposed to be the minimalist version
anyway soundstage opened up a little more, clarity, focus etc
thats not really that surprising after all i was dumping all the front end digital noise on + vref
As im a big fan of providing exceptionally clean power to clocks
for fun i bridged a wire direct from where i inputed the 3.3v rail into the board to the clock ps pad
i wasn't expecting any improvement but the sq resolution had increased
i was so surprised i ab tested a few times to make sure

i also ran a bridge from clk gnd
i ab tested it too
it might have helped a bit but its not a big enough change to be absolutely positive, im gonna leave it there for now as it sure aint doin any harm


put the scope on the clock again the waveform is much better but not as good as id like