In master-mode it generates MCLK using PLL from system clock.abraxalito wrote: ↑Wed Jun 13, 2018 2:48 am So you mean the I2S ports have no way to run in 'slave' mode? That being sync'd to an externally driven clock input.
Yes, it can be operated in slave mode & documentation says this about transmitting in slave-mode
Which means that there is no MCLK input & it seems some logic is needed in the ESP32 to send enable signal to switch between clocks speed families depending on samplerate of audio file & also, outside the ESP32, some logic needed to generate a BCK based on samplerate, which it then uses to synch the transmission of I2S-LRCK & I2S-DATA."When I2S is configured to slave transmitting mode and this bit is set, the module will wait for the master BCK clock to enable a transmit
operation."